Skip to content

Commit

Permalink
[FIFO] remove stitched IP and rtlsim metadata after FIFO sizing
Browse files Browse the repository at this point in the history
  • Loading branch information
maltanar authored and auphelia committed Oct 29, 2024
1 parent 69df427 commit eab118d
Showing 1 changed file with 11 additions and 0 deletions.
11 changes: 11 additions & 0 deletions src/finn/transformation/fpgadataflow/set_fifo_depths.py
Original file line number Diff line number Diff line change
Expand Up @@ -439,6 +439,8 @@ def apply(self, model):
sim = verilator_fifosim(model, n_inferences)
elif backend in ["xsi", "pyxsi"]:
sim = xsi_fifosim(model, n_inferences)
else:
assert False, f"Unrecognized backend for InsertAndSetFIFODepths: {backend}"

for ind, node in enumerate(fifo_nodes):
maxcount_name = "maxcount_%d" % ind
Expand Down Expand Up @@ -494,6 +496,15 @@ def apply(self, model):
# remove shallow FIFOs
model = model.transform(RemoveShallowFIFOs())

# clean up references to stitched IP and rtlsim objects
# (the stitched IP needs to be re-done after FIFO sizing)
model.set_metadata_prop("rtlsim_trace", "")
model.set_metadata_prop("rtlsim_so", "")
model.set_metadata_prop("vivado_stitch_proj", "")
model.set_metadata_prop("wrapper_filename", "")
model.set_metadata_prop("vivado_stitch_vlnv", "")
model.set_metadata_prop("vivado_stitch_ifnames", "")

# reflect final values in attributes
for node in model.graph.node:
if not node.op_type.startswith("StreamingFIFO"):
Expand Down

0 comments on commit eab118d

Please sign in to comment.