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[MVU/VVU] Support for double-pumped DSPs #929

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[MVU/VVU] Support for double-pumped DSPs #929

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Note: this PR depends on

Adds support for double-pumped DSPs

fionnodonohoe-xlnx and others added 30 commits November 17, 2022 09:20
@fionnodonohoe-xlnx
[thresholding] pass O_BITS from top module to thresholding.sv core
8616148 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] pass C_BITS from top module to thresholding.sv core
275abad 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] create & fill in RTL template values using FINN
8849c02 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add method get_weightstream_width()
84704ed 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add method get_in/output_width()
9aa7ff3 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add method body for code_generation_ipi()
608b5da 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add method get_verilog_top_module_intf_names()
ca6e7e7 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] retrieve axilite write sequence for runtime weight pro…
7266ee9 
…gramming

Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add methods for creating weight files for each simulat…
f88bdbf 
…ion type

Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add method generate_params()
560771a 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add method for preparing a Pyverilator object for RTL …
e763bf8 
…simulation

Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add method to run rtlsim on a thresholding binary sear…
84e08f1 
…ch simulation object

Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add stubbed method for ipgen_singlenode_code()
b0be07a 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] update class name to a more consistent naming convention
30d22f8 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add fpgadataflow pytests for thresholding binary searc…
3594edd 
…h node

Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add linter fixes
0bee70d 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] add flake8 fixes
0689c6a 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] change the pytest markers to omit tests from quicktest
e9a4a7b 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] update copyright banners of files I have added/changed
41c0b4b 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@preusser
Translate byte to parameter word addressing in AXI adapter.
71ef39b
@preusser
Merge branch 'dev' into feature/thresholding_addressing
47a0cf9
@fionnodonohoe-xlnx
Merge branch 'dev' into feature/thresholding
bdd100f
@fionnodonohoe-xlnx
[thresholding] remove unused attribute
d44a66c 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] remove unnecessary HLS bug prevention check
f79b9ec 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] align methods with hlscustom class by adding in additi…
7b82de2 
…onal input parameter

Signed-off-by: Fionn O'Donohoe <[email protected]>
@fionnodonohoe-xlnx
[thresholding] replace hardcoded tcl commands with node attributes
e2816d3 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@preusser
Merge branch 'feature/thresholding' into feature/thresholding_addressing
61acc64
@preusser
Fix BIAS parameter specification.
bda05ae
@fionnodonohoe-xlnx
[thresholding] remove unused ram_style attribute
7388e76 
Signed-off-by: Fionn O'Donohoe <[email protected]>
@mmrahorovic
First changes to custom_op for RTL-based MVAU
be1503a
mmrahorovic and others added 26 commits December 3, 2023 22:56
@mmrahorovic
[stitched-ip]: minor fixes to creating valid stitched-ip with ap_clk2…
b72d00d 
…x interface
@mmrahorovic
[rtl-vvu]: add stitching support for pumped compute, minor fix to seg…
04f5863 
…ment length estimation
@preusser @mmrahorovic
Prevent output register slice from operating in unnecessary ping-pong…
9b80ac1 
… mode.
@mmrahorovic
[mvu vvu axi]: verilator BLKLOOPINIT-error workaround
60f483a
@mmrahorovic
[mvu vvu axi]: sign extend output tdata (byte-aligned)
23fb64f
@mmrahorovic
[mvu-rtl]: default seglen to 1 for now
fdca45b
@mmrahorovic
update test config
45074d9
@mmrahorovic
updated test config
0ed3681
@mmrahorovic
[rtlsim]: use pyverilator util functions
c396425
@mmrahorovic
[mvu vvu axi]: fix multiple driver error
538852d
@preusser
Mitigate hold time issues on feed from fast clock net.
7e5306c
@mmrahorovic
toggle P and Vld only when no backpressure is applied
256931f
@mmrahorovic
change naming
020c4e0
@preusser
Reworking pumped DSP integration with simplified enable computation.
7e12ae4
@mmrahorovic
[rtlsim]: use pyverilator util functions
6e98bac
@mmrahorovic
[mvu vvu axi]: sign extend output tdata (byte-aligned)
5dd74ad
@mmrahorovic
[mvu core]: dsp48 convert unpacked array to packed array to work arou…
b20410b 
…nd limitation on max array indices in Verilator
@mmrahorovic
[mvu axi]: update list of deduced parameters
1c2cc0c
@mmrahorovic
[mvu custom-op]: remove lut-based implementation and update compute c…
eeb3cea 
…ore selection
@mmrahorovic
[mvu axi]: remove LUT-based compute core
0813d14
@mmrahorovic
[hls custom-op]: enable reset in sim
4892d66
@mmrahorovic
[test mvu rtl]: updated test flow (DSP58 only)
44f6e0f
@mmrahorovic
[mvu vvu axi]: reworked flow control and backpressure handling by tpr…
9b2cceb 
…eusser
@preusser
Adding DSP48E1 support for 8-bit compute. Todo: finer core differenti…
ee9f027 
…ation to select DSP48E2 explicitly again.
@preusser
Adding DSP48E1 support for 4-bit compute. Todo: finer core differenti…
3ab8296 
…ation to select DSP48E2 explicitly again.
@mmrahorovic
Merge remote-tracking branch 'origin/feature/dsp_packing' into featur…
d5cd44c 
…e/dsp_pumping
This was referenced Feb 7, 2024
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@mmrahorovic mmrahorovic closed this Feb 8, 2024
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5 participants
@mmrahorovic @fionnodonohoe-xlnx @preusser @auphelia @maltanar