Merge branch 'aie-public' into runner

.github/workflows/amd-aie-distro.yml

@@ -154,6 +154,8 @@ jobs:
         include:
           - OS: ubuntu-20.04
             ARCH: x86_64
+          - OS: windows-2019
+            ARCH: AMD64
 
     defaults:
       run:
@@ -211,7 +213,7 @@ jobs:
         LLVM_AIE_PROJECT_COMMIT=${{ needs.settings.outputs.LLVM_AIE_PROJECT_COMMIT }}
         gh api -H "Accept: application/vnd.github+json" -H "X-GitHub-Api-Version: 2022-11-28" \
           repos/Xilinx/llvm-aie/zipball/$LLVM_AIE_PROJECT_COMMIT > llvm-aie.zip
-        unzip -q llvm-aie.zip
+        unzip -qq llvm-aie.zip
         rm -rf llvm-aie.zip
         mv Xilinx-llvm-aie-* llvm-aie
 

.github/workflows/amd_aie_releases/scripts/apply_patches.sh

@@ -3,7 +3,6 @@ set -uxo pipefail
 
 # note that space before slash is important
 PATCHES="\
-mscv \
 "
 
 if [[ x"${APPLY_PATCHES:-true}" == x"true" ]]; then

.github/workflows/amd_aie_releases/setup.py

@@ -1,11 +1,11 @@
-import shutil
-from datetime import datetime
 import os
 import platform
 import re
+import shutil
 import subprocess
 import sys
-from pathlib import Path, PureWindowsPath
+from datetime import datetime
+from pathlib import Path
 from pprint import pprint
 
 from setuptools import Extension, setup
@@ -49,8 +49,6 @@ def build_extension(self, ext: CMakeExtension) -> None:
         cmake_args = [
             f"-B{build_temp}",
             f"-G {cmake_generator}",
-            "-DLLVM_BUILD_LLVM_DYLIB=ON",
-            "-DLLVM_LINK_LLVM_DYLIB=ON",
             "-DLLVM_BUILD_BENCHMARKS=OFF",
             "-DLLVM_BUILD_EXAMPLES=OFF",
             f"-DLLVM_BUILD_TESTS={RUN_TESTS}",
@@ -75,10 +73,14 @@ def build_extension(self, ext: CMakeExtension) -> None:
             f"-DCMAKE_INSTALL_PREFIX={install_dir}",
             f"-DCMAKE_LIBRARY_OUTPUT_DIRECTORY={extdir}{os.sep}",
             f"-DPython3_EXECUTABLE={PYTHON_EXECUTABLE}",
-            f"-DCMAKE_BUILD_TYPE={cfg}",  # not used on MSVC, but no harm
+            f"-DCMAKE_BUILD_TYPE={cfg}",  # not used on MSVC, but no harm,
         ]
-
-        if platform.system() == "Windows":
+        if platform.system() != "Windows":
+            cmake_args += [
+                "-DLLVM_BUILD_LLVM_DYLIB=ON",
+                "-DLLVM_LINK_LLVM_DYLIB=ON",
+            ]
+        else:
             cmake_args += [
                 "-DCMAKE_C_COMPILER=cl",
                 "-DCMAKE_CXX_COMPILER=cl",
@@ -87,6 +89,7 @@ def build_extension(self, ext: CMakeExtension) -> None:
                 "-DCMAKE_CXX_FLAGS=/MT",
                 "-DLLVM_USE_CRT_MINSIZEREL=MT",
                 "-DLLVM_USE_CRT_RELEASE=MT",
+                "-DCMAKE_POLICY_DEFAULT_CMP0091=NEW",
             ]
 
         if "CMAKE_ARGS" in os.environ:
@@ -204,7 +207,10 @@ def build_extension(self, ext: CMakeExtension) -> None:
     os.getenv("LLVM_AIE_SRC_ROOT", Path.cwd() / "llvm-aie")
 ).absolute()
 
-cmake_txt = open(LLVM_AIE_SRC_ROOT / "llvm" / "CMakeLists.txt").read()
+cmake_version_path = Path("llvm-aie/cmake/Modules/LLVMVersion.cmake")
+if not cmake_version_path.exists():
+    cmake_version_path = Path("llvm-aie/llvm/CMakeLists.txt")
+cmake_txt = open(cmake_version_path).read()
 llvm_version = []
 for v in ["LLVM_VERSION_MAJOR", "LLVM_VERSION_MINOR", "LLVM_VERSION_PATCH"]:
     vn = re.findall(rf"set\({v} (\d+)\)", cmake_txt)

clang/cmake/caches/Peano-AIE-runtime-libraries.cmake

@@ -13,6 +13,7 @@ set(LLVM_ENABLE_RUNTIMES
       libc
     CACHE STRING "")
 set(LLVM_LIBC_FULL_BUILD ON CACHE BOOL "")
+set(LLVM_FORCE_BUILD_RUNTIME "libc" CACHE STRING "")
 
 set(LLVM_BUILTIN_TARGETS "aie-none-unknown-elf;aie2-none-unknown-elf" CACHE STRING "")
 set(LLVM_RUNTIME_TARGETS "${LLVM_BUILTIN_TARGETS}" CACHE STRING "")

llvm/include/llvm/Target/AIETarget.td

@@ -20,15 +20,18 @@ class PreSchedInstExpansion<Instruction Target, Instruction Barrier> {
 }
 
 // Scheduling information for instructions that touch memory.
-class MemoryCycles<int First, int Last = -1> {
+class MemoryCycles<list<int> MemCycles> {
+  // Cycles in which memory is accessed 
+  list<int> MemCyclesList = MemCycles;
+
   // Cycle for the first load or store to memory.
-  int FirstCycle = First;
+  int FirstCycle = !head(MemCycles);
 
   // Cycle for the last load or store to memory. This is typically the same as
   // FirstCycle, except for instructions that are read-modify-write. In that
   // case, the instruction touches memory twice, and LastCycle would be
   // different from FirstCycle.
-  int LastCycle = Last;
+  int LastCycle = !if(!empty(!tail(MemCycles)), !head(MemCycles), MemCycles[!sub(!size(MemCycles),1)]);
 }
 
 // An extension of InstrItinData that is able to store MemoryCycles
@@ -39,6 +42,6 @@ class MemInstrItinData<InstrItinClass Class, list<InstrStage> stages,
                        list<Bypass> bypasses = [], int uops = 1> :
     InstrItinData<Class, stages, operandcycles, bypasses, uops> {
   int FirstMemCycle = MemCycles.FirstCycle;
-  int LastMemCycle = !if(!lt(MemCycles.LastCycle, 0),
-                         FirstMemCycle, MemCycles.LastCycle);
+  int LastMemCycle = MemCycles.LastCycle;
+  list<int> MemCyclesList = MemCycles.MemCyclesList;
 }

llvm/lib/Target/AIE/AIE2AddrSpace.h

@@ -0,0 +1,46 @@
+//===-- AIE2AddrSpace.h - Define Address Space for AIEngine V2 ---*- C++-*-===//
+//
+// This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the AIEngine V2 Address Space and DM banks
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SUPPORT_AIE2ADDRSPACE_H
+#define LLVM_SUPPORT_AIE2ADDRSPACE_H
+
+namespace llvm {
+
+namespace AIE2 {
+
+enum class AddressSpaces {
+  none, // Default address space
+  PM,   // Address space for Program Memory (PM)
+  DM,   // Address space for Data Memory(DM) includes Bank A, B, C, D
+  DM_test,
+  stack, // Address space for stack
+  a,     // Address space for DM Bank A
+  b,     // Address space for DM Bank B
+  c,     // Address space for DM Bank C
+  d,     // Address space for DM Bank D
+  ab,    // Address space for DM Bank A and B
+  ac,    // Address space for DM Bank A and C
+  ad,    // Address space for DM Bank A and D
+  bc,    // Address space for DM Bank B and C
+  bd,    // Address space for DM Bank B and D
+  cd,    // Address space for DM Bank C and D
+  TM     // Address space for TM (Tile Memory)
+};
+
+enum class AIEBanks { A, B, C, D, TileMemory };
+
+} // end namespace AIE2
+} // end namespace llvm
+
+#endif // LLVM_SUPPORT_AIE2ADDRSPACE_H

llvm/lib/Target/AIE/AIE2InstrInfo.cpp

@@ -969,6 +969,7 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
       SubRegSplit(AIE2::sub_hi_dim_then_sub_dim_count)};
 
   switch (Opcode) {
+  case AIE2::VLD_2D_pseudo:
   case AIE2::LDA_2D_dmv_lda_q:
   case AIE2::LDA_2D_dms_lda:
   case AIE2::LDA_2D_S8_dmhb_lda:
@@ -995,6 +996,7 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
   case AIE2::LDA_3D_S16_dmhb_lda:
   case AIE2::LDA_3D_U8_dmhb_lda:
   case AIE2::LDA_3D_U16_dmhb_lda:
+  case AIE2::VLD_3D_pseudo:
   case AIE2::VLDA_3D_dmw_lda_w:
   case AIE2::VLDA_3D_dmw_lda_am:
   case AIE2::VLDA_3D_CONV_FP32_BF16:

llvm/lib/Target/AIE/AIE2InstrInfo.h

@@ -95,6 +95,8 @@ class AIE2InstrInfo : public AIE2GenInstrInfo {
   int getMinLastMemoryCycle() const override;
   int getMaxLastMemoryCycle() const override;
 
+  SmallVector<int, 2> getMemoryCycles(unsigned SchedClass) const override;
+
   SmallVector<TiedRegOperands, 4>
   getTiedRegInfo(unsigned Opcode) const override;
 

llvm/lib/Target/AIE/AIE2InstrInfo.td

@@ -367,6 +367,7 @@ include "AIE2GenInstrInfo.td"
 include "AIE2CompositeFormats.td"
 // Manual fixes to the auto-generated files
 include "AIE2GenFixupInstrInfo.td"
+include "AIE2MultiSlotPseudoInstrInfo.td"
 
 //Intrinsics
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
@@ -584,8 +585,8 @@ class Split2DInstr<Instruction RealInst, int opidx> : SplitPseudo<RealInst,
 foreach instr = [VLDA_2D_dmw_lda_w, VLDA_2D_dmw_lda_am, VLDA_2D_CONV_FP32_BF16,
                  VLDB_2D, VLDB_2D_128, LDA_2D_dmv_lda_q, VLDB_2D_UNPACK_S8_S4,
                  VLDB_2D_UNPACK_S16_S8, VLDB_2D_UNPACK_D8_D4, VLDB_2D_UNPACK_D16_D8,
-                 VST_2D_dmw_sts_w, VST_2D_dmw_sts_am, VST_2D_128, ST_2D_dmv_sts_q,
-                 LDA_2D_dms_lda, LDA_2D_S8_dmhb_lda, LDA_2D_U8_dmhb_lda,
+                 VLD_2D_pseudo, VST_2D_dmw_sts_w, VST_2D_dmw_sts_am, VST_2D_128,
+                 ST_2D_dmv_sts_q, LDA_2D_dms_lda, LDA_2D_S8_dmhb_lda, LDA_2D_U8_dmhb_lda,
                  LDA_2D_S16_dmhb_lda, LDA_2D_U16_dmhb_lda,
                  ST_2D_dms_sts, ST_2D_S8, ST_2D_S16] in
     def instr # _split : Split2DInstr<instr, /*opidx=*/4>;
@@ -608,8 +609,8 @@ class Split3DInstr<Instruction RealInst, int opidx> : SplitPseudo<RealInst,
 foreach instr = [VLDA_3D_dmw_lda_w, VLDA_3D_dmw_lda_am, VLDA_3D_CONV_FP32_BF16,
                  VLDB_3D, VLDB_3D_128, LDA_3D_dmv_lda_q, VLDB_3D_UNPACK_S8_S4,
                  VLDB_3D_UNPACK_S16_S8, VLDB_3D_UNPACK_D8_D4, VLDB_3D_UNPACK_D16_D8,
-                 VST_3D_dmw_sts_w, VST_3D_dmw_sts_am, VST_3D_128, ST_3D_dmv_sts_q,
-                 LDA_3D_dms_lda, LDA_3D_S8_dmhb_lda, LDA_3D_U8_dmhb_lda,
+                 VLD_3D_pseudo, VST_3D_dmw_sts_w, VST_3D_dmw_sts_am, VST_3D_128, 
+                 ST_3D_dmv_sts_q, LDA_3D_dms_lda, LDA_3D_S8_dmhb_lda, LDA_3D_U8_dmhb_lda,
                  LDA_3D_S16_dmhb_lda, LDA_3D_U16_dmhb_lda,
                  ST_3D_dms_sts, ST_3D_S8, ST_3D_S16] in
     def instr # _split : Split3DInstr<instr, /*opidx=*/5>;
@@ -625,5 +626,4 @@ foreach instr = [VST_3D_SRS_D8_S32, VST_3D_SRS_D16_S64, VST_3D_SRS_D16_S32,
                  PADDA_3D, PADDB_3D, PADDS_3D] in
     def instr # _split : Split3DInstr<instr, /*opidx=*/4>;
 
-include "AIE2MultiSlotPseudoInstrInfo.td"
 include "AIE2InstrPatterns.td"

llvm/lib/Target/AIE/AIE2InstrPatterns.td

@@ -242,11 +242,8 @@ def : PartWordStPat<truncstorei16, ST_S16_ag_idx_imm, Ty, eR>;
 }
 
 // 3.2 VLD - Vector Load
-class VectorLdPat<ValueType ResType, AIE2Inst Inst = VLDA_dmw_lda_w_ag_idx_imm>
-    : Pat<(ResType (load eP:$rs1)), (Inst eP:$rs1, (i20 0))>;
-
 // 1024-bit vector load
-class VectorLdPat1024<ValueType Rtype, ValueType type, AIE2Inst Inst = VLDA_dmw_lda_w_ag_idx_imm>
+class VectorLdPat1024<ValueType Rtype, ValueType type, AIE2Inst Inst = VLD_idx_imm_3x32_pseudo>
     : Pat<(Rtype (load eP:$rs1)),
              (INSERT_SUBREG
                (INSERT_SUBREG