[AIE2] Add missing aie2_v8accfloat and tests.

Xilinx · May 20, 2024 · af3a6ab · af3a6ab
1 parent b3bf84d
commit af3a6ab
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Showing 3 changed files with 32 additions and 0 deletions.
diff --git a/llvm/lib/Target/AIE/AIE2InstructionSelector.cpp b/llvm/lib/Target/AIE/AIE2InstructionSelector.cpp
@@ -565,6 +565,7 @@ bool AIE2InstructionSelector::select(MachineInstr &I) {
     case Intrinsic::aie2_v16bfloat16:
     case Intrinsic::aie2_v32bfloat16:
     case Intrinsic::aie2_v64bfloat16:
+    case Intrinsic::aie2_v8accfloat:
     case Intrinsic::aie2_v16accfloat:
     case Intrinsic::aie2_v32accfloat:
     case Intrinsic::aie2_v8float:

diff --git a/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-undef-accfloat.mir b/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-undef-accfloat.mir
@@ -7,6 +7,22 @@
 # (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
 # RUN: llc -mtriple aie2 -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
 
+---
+name:            v8accfloat_undef
+alignment:       16
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: v8accfloat_undef
+    ; CHECK: [[DEF:%[0-9]+]]:acc256 = IMPLICIT_DEF
+    ; CHECK-NEXT: $amll0 = COPY [[DEF]]
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $amll0
+    %0:accregbank(<4 x s64>) = G_INTRINSIC intrinsic(@llvm.aie2.v8accfloat)
+    $amll0 = COPY %0:accregbank(<4 x s64>)
+    PseudoRET implicit $lr, implicit $amll0
+...
+
 ---
 name:            v16accfloat_undef
 alignment:       16

diff --git a/llvm/test/CodeGen/AIE/aie2/undef_vectors.ll b/llvm/test/CodeGen/AIE/aie2/undef_vectors.ll
@@ -342,6 +342,21 @@ entry:
   ret <16 x i64> %0
 }
 
+define <4 x i64> @test_undef_v8accfloat() {
+; CHECK-LABEL: test_undef_v8accfloat:
+; CHECK:         .p2align 4
+; CHECK-NEXT:  // %bb.0: // %entry
+; CHECK-NEXT:    nopa ; ret lr
+; CHECK-NEXT:    nop // Delay Slot 5
+; CHECK-NEXT:    nop // Delay Slot 4
+; CHECK-NEXT:    nop // Delay Slot 3
+; CHECK-NEXT:    nop // Delay Slot 2
+; CHECK-NEXT:    nop // Delay Slot 1
+entry:
+  %0 = tail call noundef <4 x i64> @llvm.aie2.v8accfloat()
+  ret <4 x i64> %0
+}
+
 define <8 x i64> @test_undef_v16accfloat() {
 ; CHECK-LABEL: test_undef_v16accfloat:
 ; CHECK:         .p2align 4