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[AIE2P] Extend AIESubRegConstrainer for FIFO ops
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Covering also *InstrInfo required changes.
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@andcarminati
andcarminati committed Jan 24, 2025
1 parent af6f54b commit fa66f1d
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Showing 18 changed files with 953 additions and 653 deletions.
58 changes: 29 additions & 29 deletions llvm/lib/Target/AIE/AIE2InstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//
//
Expand Down Expand Up @@ -1207,8 +1207,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::LDA_3D_dmv_lda_q:
case AIE2::LDA_3D_dms_lda:
case AIE2::LDA_3D_S8_dmhb_lda:
Expand All @@ -1231,8 +1231,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::VLDA_2D_UPS_S32_D16:
case AIE2::VLDA_2D_UPS_S64_D32:
case AIE2::VLDA_2D_UPS_S32_D8:
Expand All @@ -1244,8 +1244,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::VLDA_3D_UPS_S32_D16:
case AIE2::VLDA_3D_UPS_S64_D32:
case AIE2::VLDA_3D_UPS_S32_D8:
Expand All @@ -1260,8 +1260,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/6, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/6, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::ST_2D_dmv_sts_q:
case AIE2::VST_2D_dmw_sts_am:
case AIE2::VST_2D_dmw_sts_w:
Expand All @@ -1272,17 +1272,17 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::VST_2D_PACK_D4_D8:
case AIE2::VST_2D_PACK_D8_D16:
case AIE2::VST_2D_PACK_S4_S8:
case AIE2::VST_2D_PACK_S8_S16:
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::ST_3D_dmv_sts_q:
case AIE2::VST_3D_dmw_sts_w:
case AIE2::VST_3D_128:
Expand All @@ -1296,8 +1296,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/5, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::VST_3D_PACK_D4_D8:
case AIE2::VST_3D_PACK_D8_D16:
case AIE2::VST_3D_PACK_S4_S8:
Expand All @@ -1308,23 +1308,23 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::VST_CONV_2D_BF16_FP32:
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::VST_CONV_3D_BF16_FP32:
// Constraints = "$count_lo_out=$mod.sub_dim_count,
// $count_hi_out=$mod.sub_hi_dim_then_sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::VST_2D_SRS_D8_S32:
case AIE2::VST_2D_SRS_D16_S64:
case AIE2::VST_2D_SRS_D16_S32:
Expand All @@ -1336,8 +1336,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
/*SrcOp=*/{{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::VST_3D_SRS_D8_S32:
case AIE2::VST_3D_SRS_D16_S64:
case AIE2::VST_3D_SRS_D16_S32:
Expand All @@ -1352,17 +1352,17 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
/*DstOps=*/{
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
/*SrcOp=*/{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
case AIE2::PADDA_2D:
case AIE2::PADDB_2D:
case AIE2::PADDS_2D:
// Constraints = "$count_out=$mod.sub_dim_count"
return {TiedRegOperands{
/*DstOps=*/{{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count}},
/*SrcOp=*/
{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}};
{{/*OpIdx=*/3, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split2DReg}}}};
case AIE2::PADDA_3D:
case AIE2::PADDB_3D:
case AIE2::PADDS_3D:
Expand All @@ -1373,8 +1373,8 @@ AIE2InstrInfo::getTiedRegInfo(unsigned Opcode) const {
{/*OpIdx=*/1, /*SubRegIdx=*/AIE2::sub_dim_count},
{/*OpIdx=*/2, /*SubRegIdx=*/AIE2::sub_hi_dim_then_sub_dim_count}},
/*SrcOp=*/
{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}};
{{/*OpIdx=*/4, /*SubRegIdx=*/AIE2::NoSubRegister,
/*SubRegsSplit=*/Split3DReg}}}};
default:
return {};
}
Expand Down
67 changes: 58 additions & 9 deletions llvm/lib/Target/AIE/AIEBaseInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//
//
Expand Down Expand Up @@ -750,9 +750,24 @@ bool AIEBaseInstrInfo::verifyTiedRegisters(const MachineInstr &MI,
StringRef &ErrInfo) const {
const TargetSubtargetInfo &ST = MI.getMF()->getSubtarget();
const TargetRegisterInfo &TRI = *ST.getRegisterInfo();
auto VerifyTiedReg = [&](const MachineOperand &Op,
const MachineOperand &TiedOp,
unsigned ExpectedSubReg) {
auto VerifyTiedReg = [&](const MachineInstr &MI,
const OperandSubRegMapping &DstOp,
const OperandSubRegMapping &SrcOp) {
const MachineOperand &Op = MI.getOperand(DstOp.OpIdx);
const MachineOperand &TiedOp = MI.getOperand(SrcOp.OpIdx);
unsigned ExpectedSubReg = DstOp.SubRegIdx;

if (SrcOp.SubRegIdx) {
if (DstOp.SubRegIdx && (SrcOp.SubRegIdx != DstOp.SubRegIdx)) {
// We are comparing incompatible registers (invalid src/dst pair), if
// something is wrong here, base verifier will take care.
return true;
}
// We have a valid pair, but one register is not subreg of the
// other.
ExpectedSubReg = 0;
}

if (!Op.isReg() || !TiedOp.isReg()) {
ErrInfo = "Tied operand must be a register";
return false;
Expand All @@ -771,16 +786,50 @@ bool AIEBaseInstrInfo::verifyTiedRegisters(const MachineInstr &MI,
ErrInfo = "Tied register is renamable";
return false;
}
return TargetInstrInfo::verifyInstruction(MI, ErrInfo);
return true;
};

auto VerifyIfBelogToSameSuperReg = [&](const MachineInstr &MI,
const TiedRegOperands &TiedRegs) {
Register SuperReg = 0;

if (!TiedRegs.NewSuperClass)
return true;

for (auto &OpSubMapping : TiedRegs.SrcOps) {
const Register SrcReg = MI.getOperand(OpSubMapping.OpIdx).getReg();
if (!Register::isPhysicalRegister(SrcReg))
continue;
const Register ActualSuperReg = TRI.getMatchingSuperReg(
SrcReg, OpSubMapping.SubRegIdx, TiedRegs.NewSuperClass);
if (!SuperReg) {
SuperReg = ActualSuperReg;
continue;
}
if (ActualSuperReg != SuperReg) {
ErrInfo =
"Tied physical registers must match to the same super register";
return false;
}
}
return true;
};

for (const TiedRegOperands &Regs : getTiedRegInfo(MI)) {
const MachineOperand &SrcOp = MI.getOperand(Regs.SrcOp.OpIdx);
if (!VerifyTiedReg(SrcOp, SrcOp, Regs.SrcOp.SubRegIdx))

// Verify if a set of src regs compose the same superreg.
if (!VerifyIfBelogToSameSuperReg(MI, Regs))
return false;
for (const OperandSubRegMapping &DstOp : Regs.DstOps) {
if (!VerifyTiedReg(MI.getOperand(DstOp.OpIdx), SrcOp, DstOp.SubRegIdx))

for (const OperandSubRegMapping &SrcOpMap : Regs.SrcOps) {
if (!VerifyTiedReg(MI, SrcOpMap, SrcOpMap)) {
return false;
}
for (const OperandSubRegMapping &DstOpMap : Regs.DstOps) {
if (!VerifyTiedReg(MI, DstOpMap, SrcOpMap)) {
return false;
}
}
}
}
return true;
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AIE/AIEBaseInstrInfo.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
//
//===----------------------------------------------------------------------===//
//
Expand Down
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