[AIEX] Delay metalizing of multi-slot until iterative scheduling is converged

[krishnamtibrewala]

This PR allows Multi-Slot Instr. to be used during iterative scheduling of loop.
Before this PR we were materializing Multi-Slot Instr. to selected OpCode/Slot after first iteration of iterative scheduling.
Now we wait until PostRA scheduling is converged to an acceptable schedule and we have decided to commit the schedule and move to next MBB.

• When is the materialization triggered now? : When we leave a MBB.
• Does this change depending on the region type? : The changes are agnostic to region type.
• Could you think of the case where the materialization is not triggered before moving on to another MBB? : None that I can think of

Note : Given the information of what Alternate opcode/desc was selected is stored in Hazard Recognizer for a region.
And by the time we come to the end of MBB ( i.e leaveMBB() ) we do not have access to the instance of those Hazard Recognizer, therefore we need to make the Alternate opcode/desc part of the BlockState

[krishnamtibrewala]

@martien-de-jong , @andcarminati.
Kindly review and provide an early feedback toward the approach

[andcarminati]

Hi @krishnamtibrewala, nice work! Do you have some results for the PixelShuffle*/PixelUnshuffle* benchmarks? If I remember correctly, we have some suboptimal mov desc assignments (movx should be selected instead of mova to not shift loads ups).

[martien-de-jong]

Could we have a test example where we see improvement?

[krishnamtibrewala]

Do you have some results for the PixelShuffle*/PixelUnshuffle* benchmarks? If I remember correctly, we have some suboptimal mov desc assignments (movx should be selected instead of mova to not shift loads ups).

@andcarminati I tried but I did not see any change, still investigating why.

Could we have a test example where we see improvement?

@martien-de-jong still figuring out.

Based on discussion with @gbossu we were expecting some impact but with current implementation QoR have no change.

[krishnamtibrewala]

Attached is a diff, I am still trying to figure out how things are interacting.
Also will try to come up with a smaller test case.

[andcarminati]

As a general advice, I think we should have a class to manage the description handling. We can encapsulate and use it in HazardRecognizer and InterBlockScheduling.

[gbossu]

Could you summarize what this PR does? Maybe in the PR description. I'm particularly interested in:

• When is the materialization triggered now?
• Does this change depending on the region type?
• Could you think of the case where the materialization is not triggered before moving on to another MBB?

[gbossu]

That test is unfortunately very hard to read. Could you think of something smaller that shows a diff? I'd also suggest avoiding two labels like on/off and stick to unique CHECK lines unless the test is very concise.

[krishnamtibrewala]

QoR Results are as followed, there are few regression reset all benchmarks have same QoR

Select_aie2_bf16 409 440 REGR(+7.58%)
BitwiseXor_aie2_int8 731 776 REGR(+6.16%)
BilinearInterpolation_2 996 1018 REGR(+2.21%)
BilinearInterpolation_3 996 1018 REGR(+2.21%)
BilinearInterpolation_4 996 1018 REGR(+2.21%)
BilinearInterpolation_0 780 794 REGR(+1.79%)
Conv2D_bf16_2 19089 19281 REGR(+1.01%)
Conv2D_bf16_5 19089 19281 REGR(+1.01%)
Conv2D_bf16_8 20607 20799 REGR(+0.93%)
BilinearInterpolation_1 474 478 REGR(+0.84%)
Conv2D_bf16_59 6253 6301 REGR(+0.77%)

[gbossu]

QoR Results are as followed, there are few regression reset all benchmarks have same QoR

Select_aie2_bf16 409 440 REGR(+7.58%) BitwiseXor_aie2_int8 731 776 REGR(+6.16%) BilinearInterpolation_2 996 1018 REGR(+2.21%) BilinearInterpolation_3 996 1018 REGR(+2.21%) BilinearInterpolation_4 996 1018 REGR(+2.21%) BilinearInterpolation_0 780 794 REGR(+1.79%) Conv2D_bf16_2 19089 19281 REGR(+1.01%) Conv2D_bf16_5 19089 19281 REGR(+1.01%) Conv2D_bf16_8 20607 20799 REGR(+0.93%) BilinearInterpolation_1 474 478 REGR(+0.84%) Conv2D_bf16_59 6253 6301 REGR(+0.77%)

I'm quite surprised about the results. Did you have time to investigate the regressions?

[krishnamtibrewala]

QoR Results are as followed, there are few regression reset all benchmarks have same QoR
Select_aie2_bf16 409 440 REGR(+7.58%) BitwiseXor_aie2_int8 731 776 REGR(+6.16%) BilinearInterpolation_2 996 1018 REGR(+2.21%) BilinearInterpolation_3 996 1018 REGR(+2.21%) BilinearInterpolation_4 996 1018 REGR(+2.21%) BilinearInterpolation_0 780 794 REGR(+1.79%) Conv2D_bf16_2 19089 19281 REGR(+1.01%) Conv2D_bf16_5 19089 19281 REGR(+1.01%) Conv2D_bf16_8 20607 20799 REGR(+0.93%) BilinearInterpolation_1 474 478 REGR(+0.84%) Conv2D_bf16_59 6253 6301 REGR(+0.77%)

I'm quite surprised about the results. Did you have time to investigate the regressions?

With the latest changes + 2nd Commit ([AIE2] Update VLD Multi-Slot Itinerary) of the PR there are no regressions.
The issue was how Multi-slot latency Vector Load instruction latency was treated.

[gbossu]

Can you give more details about this change? Why does this impact the postmisched? It should not be impacted by the resources of the multi-slot itinerary, because when checking or adding to the scoreboard, the final itinerary should be used.