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Set default stride value for unused dimension to be 0
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@erwei-xilinx
erwei-xilinx committed Feb 13, 2025
1 parent 3c09358 commit 42cae6e
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Showing 2 changed files with 11 additions and 11 deletions.
2 changes: 1 addition & 1 deletion mlir/lib/Conversion/AIRRtToNpuPass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -761,7 +761,7 @@ struct AIRSpecializeAIRRtDmaWrapAndStrideInAffineFor
wraps.insert(wraps.begin(), i64_one);
}
while (strides.size() < 3) {
strides.insert(strides.begin(), i64_one);
strides.insert(strides.begin(), i64_zero);
}

// Stride = 0 means repeat that dimension. If highest dimension (dim 0) is
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20 changes: 10 additions & 10 deletions mlir/test/Conversion/AIRRtToNpu/airrt_to_npu.mlir
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Expand Up @@ -255,8 +255,8 @@ module {

// CHECK-LABEL: aie.device(npu1_1col)
// CHECK: aiex.runtime_sequence @func5(%[[ARG0:.*]]: memref<8x8xi32>, %[[ARG1:.*]]: memref<8x8xi32>, %[[ARG2:.*]]: memref<8x8xi32>)
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][2, 1, 1, 32][0, 1, 1, 1]) {id = 0 : i64, metadata = @airMemcpyId4} : memref<8x8xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 32][2, 1, 1, 32][0, 1, 1, 1]) {id = 1 : i64, metadata = @airMemcpyId4} : memref<8x8xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][2, 1, 1, 32][0, 0, 0, 1]) {id = 0 : i64, metadata = @airMemcpyId4} : memref<8x8xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 32][2, 1, 1, 32][0, 0, 0, 1]) {id = 1 : i64, metadata = @airMemcpyId4} : memref<8x8xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG1]][0, 0, 0, 0][2, 2, 8, 4][0, 4, 8, 1]) {id = 2 : i64, metadata = @airMemcpyId5} : memref<8x8xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG2]][0, 0, 0, 0][2, 2, 4, 4][32, 4, 8, 1]) {id = 3 : i64, metadata = @airMemcpyId16} : memref<8x8xi32>

Expand Down Expand Up @@ -310,9 +310,9 @@ module {

// CHECK-LABEL: aie.device(npu1_1col)
// CHECK: aiex.runtime_sequence @func6(%[[ARG0:.*]]: memref<8x16xi32>, %[[ARG1:.*]]: memref<16x32xi32>, %[[ARG2:.*]]: memref<8x32xi32>)
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][2, 1, 1, 128][0, 1, 1, 1]) {id = 0 : i64, metadata = @airMemcpyId4} : memref<8x16xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG1]][0, 0, 0, 0][1, 2, 16, 16][1, 16, 32, 1]) {id = 1 : i64, metadata = @airMemcpyId5} : memref<16x32xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG2]][0, 0, 0, 0][1, 2, 8, 16][1, 16, 32, 1]) {id = 2 : i64, metadata = @airMemcpyId12} : memref<8x32xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][2, 1, 1, 128][0, 0, 0, 1]) {id = 0 : i64, metadata = @airMemcpyId4} : memref<8x16xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG1]][0, 0, 0, 0][1, 2, 16, 16][0, 16, 32, 1]) {id = 1 : i64, metadata = @airMemcpyId5} : memref<16x32xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG2]][0, 0, 0, 0][1, 2, 8, 16][0, 16, 32, 1]) {id = 2 : i64, metadata = @airMemcpyId12} : memref<8x32xi32>

#map = affine_map<()[s0] -> (s0 * 8)>
#map1 = affine_map<()[s0] -> (s0 * 16)>
Expand Down Expand Up @@ -812,10 +812,10 @@ module {

// CHECK-LABEL: aie.device(npu1_1col)
// CHECK: aiex.runtime_sequence @func18(%[[ARG0:.*]]: memref<8192x32768xi32>)
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][1, 4, 64, 64][1, 64, 32768, 1]) {id = 0 : i64, metadata = @airMemcpyId26} : memref<8192x32768xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 64, 0][1, 4, 64, 64][1, 64, 32768, 1]) {id = 1 : i64, metadata = @airMemcpyId26} : memref<8192x32768xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 128, 0][1, 4, 64, 64][1, 64, 32768, 1]) {id = 2 : i64, metadata = @airMemcpyId26} : memref<8192x32768xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 192, 0][1, 4, 64, 64][1, 64, 32768, 1]) {id = 3 : i64, metadata = @airMemcpyId26} : memref<8192x32768xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 0, 0][1, 4, 64, 64][0, 64, 32768, 1]) {id = 0 : i64, metadata = @airMemcpyId26} : memref<8192x32768xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 64, 0][1, 4, 64, 64][0, 64, 32768, 1]) {id = 1 : i64, metadata = @airMemcpyId26} : memref<8192x32768xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 128, 0][1, 4, 64, 64][0, 64, 32768, 1]) {id = 2 : i64, metadata = @airMemcpyId26} : memref<8192x32768xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %[[ARG0]][0, 0, 192, 0][1, 4, 64, 64][0, 64, 32768, 1]) {id = 3 : i64, metadata = @airMemcpyId26} : memref<8192x32768xi32>

#map = affine_map<()[s0] -> (s0 * 64)>
module {
Expand Down Expand Up @@ -973,7 +973,7 @@ module {
// Offset field with (1) for loop induction variable, (2) affine map, and (3) existing non-singleton stride.

// CHECK-LABEL: func22
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %arg0[0, 0, 0, 0][1, 2, 8, 512][1, 4096, 512, 1]) {id = 0 : i64, metadata = @airMemcpyId31} : memref<2x64x64xi32>
// CHECK: aiex.npu.dma_memcpy_nd(0, 0, %arg0[0, 0, 0, 0][1, 2, 8, 512][0, 4096, 512, 1]) {id = 0 : i64, metadata = @airMemcpyId31} : memref<2x64x64xi32>
// CHECK: aiex.npu.sync {channel = 0 : i32, column = 0 : i32, column_num = 1 : i32, direction = 0 : i32, row = 0 : i32, row_num = 1 : i32}

#map = affine_map<()[s0] -> (s0 * 64)>
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