Build: (025aecb) CPM5 RC Hardware Design Creation

pciedebug/build/html/_sources/docs/PS_PCIe_PL_PCIe_Root_Port_Driver/Versal_CPM5_PCIe_Root_Port_Design_Linux/hardware_design_creation.rst.txt

@@ -3,6 +3,87 @@
 Hardware Design Creation
 =======================
 
-    * This page is in progress and will be available soon. Please visit later.
-..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
+Launch Vivado 2024.2 tool and select “Vivado Store” from the “Tools” list.
 
+.. image:: HW_Design/img_1.jpg
+   :alt: Vivado Store Tool
+
+In the “Vivado Store”, click on the “Example Designs” tab at the top of the left, then click the “Refresh” button at the bottom left. Vivado will contact GitHub to make sure the list of example designs is up to date. Locate the “Versal CPM Bridge RP Design” in the list. If the glyph is a grey circle with a down arrow, it means the example design needs to be downloaded – proceed to download it. If the glyph is a green check with a yellow dot, it means the example design needs to be updated – proceed to update it. Once the catalog is up to date and the glyph is a green check without any other annotation, it means the example design is downloaded and up to date.
+
+.. image:: HW_Design/img_2.jpg
+   :alt: Vivado Store Example Designs
+
+Once this example design is downloaded and up to date, close the “Vivado Store” by clicking “Close”.
+
+Select “Open Example Project” from the “Quick Start” list.
+
+.. image:: HW_Design/img_3.jpg
+   :alt: Open Example Project
+
+Advance through the wizard by clicking “Next”.
+
+.. image:: HW_Design/img_4.jpg
+   :alt: Wizard Next Button
+
+Access the “Versal CPM Bridge RP Design” example project.
+
+.. image:: HW_Design/img_5.jpg
+   :alt: Versal CPM Bridge RP Design Project
+
+Based on earlier steps, the example project should be showing as downloaded and up to date. With the example project selected, the “Description” should show basic information about the example project. Advance to the next step by clicking “Next”.
+
+Specify a project name and project location.
+
+.. image:: HW_Design/img_6.jpg
+   :alt: Project Name and Location
+
+Select the “Versal VPK120 Evaluation Platform”, switch part to xcvp1202-vsva2785-2MHP-e-S and click “Next”.
+
+.. image:: HW_Design/img_7.jpg
+   :alt: Select Evaluation Platform
+
+Ensure that CPM5 is auto-selected. Select "CPM5 PCIe Controller0 Gen4x8 RootPort Design" as CPM5_Preset and click “Next”.
+
+.. image:: HW_Design/img_8.jpg
+   :alt: CPM5 PCIe Controller Configuration
+
+Review the Project Summary to confirm that the part and product family selections are correct. Advance through the wizard by clicking “Finish”.
+
+.. image:: HW_Design/img_9.jpg
+   :alt: Project Summary Review
+
+Wait until the project creation, file import, and hierarchy update has completed. This may take a few minutes.
+
+No changes need to be made on any portion of this design. Feel free to investigate any properties of the IP Blocks in the design to learn more about the details of this example design.
+
+Below is the block diagram of the "cpm_rp.bd":
+
+.. image:: HW_Design/img_10.jpg
+   :alt: cpm_rp.bd Block Diagram
+
+From “Flow Navigator” click “Generate Device Image”
+
+.. image:: HW_Design/img_11.jpg
+   :alt: Generate Device Image
+
+Export Hardware Design to Generate .xsa file for the Project
+
+From File menu, select "Export" --> "Export Hardware"
+
+.. image:: HW_Design/img_12.jpg
+   :alt: Export Hardware Menu
+
+Select “Next”, and “Include Device Image”.
+
+.. image:: HW_Design/img_13.jpg
+   :alt: Include Device Image
+
+Create a .xsa file name and select export location. By default, the export location is inside of the project directory made earlier. Click on Next.
+
+.. image:: HW_Design/img_14.jpg
+   :alt: File Export Location
+
+Click on Finish.
+
+.. image:: HW_Design/img_15.jpg
+   :alt: Finish Export Process

pciedebug/build/html/docs/PS_PCIe_PL_PCIe_Root_Port_Driver/Versal_CPM5_PCIe_Root_Port_Design_Linux/hardware_design_creation.html

@@ -133,11 +133,41 @@
 
   <div class="section" id="hardware-design-creation">
 <span id="ps-pcie-pl-pcie-driver-debug-checklist"></span><h1>Hardware Design Creation<a class="headerlink" href="#hardware-design-creation" title="Permalink to this heading">¶</a></h1>
-<blockquote>
-<div><ul class="simple">
-<li><p>This page is in progress and will be available soon. Please visit later.</p></li>
-</ul>
-</div></blockquote>
+<p>Launch Vivado 2024.2 tool and select “Vivado Store” from the “Tools” list.</p>
+<img alt="Vivado Store Tool" src="../../../_images/img_1.jpg" />
+<p>In the “Vivado Store”, click on the “Example Designs” tab at the top of the left, then click the “Refresh” button at the bottom left. Vivado will contact GitHub to make sure the list of example designs is up to date. Locate the “Versal CPM Bridge RP Design” in the list. If the glyph is a grey circle with a down arrow, it means the example design needs to be downloaded – proceed to download it. If the glyph is a green check with a yellow dot, it means the example design needs to be updated – proceed to update it. Once the catalog is up to date and the glyph is a green check without any other annotation, it means the example design is downloaded and up to date.</p>
+<img alt="Vivado Store Example Designs" src="../../../_images/img_2.jpg" />
+<p>Once this example design is downloaded and up to date, close the “Vivado Store” by clicking “Close”.</p>
+<p>Select “Open Example Project” from the “Quick Start” list.</p>
+<img alt="Open Example Project" src="../../../_images/img_3.jpg" />
+<p>Advance through the wizard by clicking “Next”.</p>
+<img alt="Wizard Next Button" src="../../../_images/img_4.jpg" />
+<p>Access the “Versal CPM Bridge RP Design” example project.</p>
+<img alt="Versal CPM Bridge RP Design Project" src="../../../_images/img_5.jpg" />
+<p>Based on earlier steps, the example project should be showing as downloaded and up to date. With the example project selected, the “Description” should show basic information about the example project. Advance to the next step by clicking “Next”.</p>
+<p>Specify a project name and project location.</p>
+<img alt="Project Name and Location" src="../../../_images/img_6.jpg" />
+<p>Select the “Versal VPK120 Evaluation Platform”, switch part to xcvp1202-vsva2785-2MHP-e-S and click “Next”.</p>
+<img alt="Select Evaluation Platform" src="../../../_images/img_7.jpg" />
+<p>Ensure that CPM5 is auto-selected. Select “CPM5 PCIe Controller0 Gen4x8 RootPort Design” as CPM5_Preset and click “Next”.</p>
+<img alt="CPM5 PCIe Controller Configuration" src="../../../_images/img_8.jpg" />
+<p>Review the Project Summary to confirm that the part and product family selections are correct. Advance through the wizard by clicking “Finish”.</p>
+<img alt="Project Summary Review" src="../../../_images/img_9.jpg" />
+<p>Wait until the project creation, file import, and hierarchy update has completed. This may take a few minutes.</p>
+<p>No changes need to be made on any portion of this design. Feel free to investigate any properties of the IP Blocks in the design to learn more about the details of this example design.</p>
+<p>Below is the block diagram of the “cpm_rp.bd”:</p>
+<img alt="cpm_rp.bd Block Diagram" src="../../../_images/img_10.jpg" />
+<p>From “Flow Navigator” click “Generate Device Image”</p>
+<img alt="Generate Device Image" src="../../../_images/img_11.jpg" />
+<p>Export Hardware Design to Generate .xsa file for the Project</p>
+<p>From File menu, select “Export” –&gt; “Export Hardware”</p>
+<img alt="Export Hardware Menu" src="../../../_images/img_12.jpg" />
+<p>Select “Next”, and “Include Device Image”.</p>
+<img alt="Include Device Image" src="../../../_images/img_13.jpg" />
+<p>Create a .xsa file name and select export location. By default, the export location is inside of the project directory made earlier. Click on Next.</p>
+<img alt="File Export Location" src="../../../_images/img_14.jpg" />
+<p>Click on Finish.</p>
+<img alt="Finish Export Process" src="../../../_images/img_15.jpg" />
 </div>
 
 

pciedebug/source/docs/PS_PCIe_PL_PCIe_Root_Port_Driver/Versal_CPM5_PCIe_Root_Port_Design_Linux/hardware_design_creation.rst

@@ -3,6 +3,87 @@
 Hardware Design Creation
 =======================
 
-    * This page is in progress and will be available soon. Please visit later.
-..            *   The PCI Express Controller Programing Model section in UG1085 summarizes programming of the PCI Express controller for Endpoint and Root Port mode operations. Review that section to make sure programming of the PS-GT Transceiver Interface, IOU for Reset Pin, PCI Express Controller and Bridge initialization has been done correctly.
+Launch Vivado 2024.2 tool and select “Vivado Store” from the “Tools” list.
 
+.. image:: HW_Design/img_1.jpg
+   :alt: Vivado Store Tool
+
+In the “Vivado Store”, click on the “Example Designs” tab at the top of the left, then click the “Refresh” button at the bottom left. Vivado will contact GitHub to make sure the list of example designs is up to date. Locate the “Versal CPM Bridge RP Design” in the list. If the glyph is a grey circle with a down arrow, it means the example design needs to be downloaded – proceed to download it. If the glyph is a green check with a yellow dot, it means the example design needs to be updated – proceed to update it. Once the catalog is up to date and the glyph is a green check without any other annotation, it means the example design is downloaded and up to date.
+
+.. image:: HW_Design/img_2.jpg
+   :alt: Vivado Store Example Designs
+
+Once this example design is downloaded and up to date, close the “Vivado Store” by clicking “Close”.
+
+Select “Open Example Project” from the “Quick Start” list.
+
+.. image:: HW_Design/img_3.jpg
+   :alt: Open Example Project
+
+Advance through the wizard by clicking “Next”.
+
+.. image:: HW_Design/img_4.jpg
+   :alt: Wizard Next Button
+
+Access the “Versal CPM Bridge RP Design” example project.
+
+.. image:: HW_Design/img_5.jpg
+   :alt: Versal CPM Bridge RP Design Project
+
+Based on earlier steps, the example project should be showing as downloaded and up to date. With the example project selected, the “Description” should show basic information about the example project. Advance to the next step by clicking “Next”.
+
+Specify a project name and project location.
+
+.. image:: HW_Design/img_6.jpg
+   :alt: Project Name and Location
+
+Select the “Versal VPK120 Evaluation Platform”, switch part to xcvp1202-vsva2785-2MHP-e-S and click “Next”.
+
+.. image:: HW_Design/img_7.jpg
+   :alt: Select Evaluation Platform
+
+Ensure that CPM5 is auto-selected. Select "CPM5 PCIe Controller0 Gen4x8 RootPort Design" as CPM5_Preset and click “Next”.
+
+.. image:: HW_Design/img_8.jpg
+   :alt: CPM5 PCIe Controller Configuration
+
+Review the Project Summary to confirm that the part and product family selections are correct. Advance through the wizard by clicking “Finish”.
+
+.. image:: HW_Design/img_9.jpg
+   :alt: Project Summary Review
+
+Wait until the project creation, file import, and hierarchy update has completed. This may take a few minutes.
+
+No changes need to be made on any portion of this design. Feel free to investigate any properties of the IP Blocks in the design to learn more about the details of this example design.
+
+Below is the block diagram of the "cpm_rp.bd":
+
+.. image:: HW_Design/img_10.jpg
+   :alt: cpm_rp.bd Block Diagram
+
+From “Flow Navigator” click “Generate Device Image”
+
+.. image:: HW_Design/img_11.jpg
+   :alt: Generate Device Image
+
+Export Hardware Design to Generate .xsa file for the Project
+
+From File menu, select "Export" --> "Export Hardware"
+
+.. image:: HW_Design/img_12.jpg
+   :alt: Export Hardware Menu
+
+Select “Next”, and “Include Device Image”.
+
+.. image:: HW_Design/img_13.jpg
+   :alt: Include Device Image
+
+Create a .xsa file name and select export location. By default, the export location is inside of the project directory made earlier. Click on Next.
+
+.. image:: HW_Design/img_14.jpg
+   :alt: File Export Location
+
+Click on Finish.
+
+.. image:: HW_Design/img_15.jpg
+   :alt: Finish Export Process