abstract: test -init

YosysHQ · Feb 19, 2025 · 5bd1861 · 5bd1861
1 parent 925c617
commit 5bd1861
Showing 1 changed file with 39 additions and 0 deletions.
diff --git a/tests/various/abstract_init.ys b/tests/various/abstract_init.ys
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+design -reset
+read_verilog <<EOT
+module foo (CLK, Q, QQQ);
+	input CLK;
+	output reg QQQ;
+	output reg Q = 1'b1;
+	assign QQQ = Q;
+	always @(posedge CLK)
+		Q <= ~Q;
+endmodule
+EOT
+
+proc
+opt_expr
+opt_dff
+select -assert-count 1 w:Q a:init %i
+abstract -init w:QQQ
+check -assert
+select -assert-count 0 w:Q a:init %i
+
+design -reset
+read_verilog <<EOT
+module foo (CLK, Q, QQQ);
+	input CLK;
+	output reg QQQ;
+	output reg [1:0] Q = 1'b1;
+	assign QQQ = Q;
+	always @(posedge CLK)
+		Q <= ~Q;
+endmodule
+EOT
+
+proc
+opt_expr
+opt_dff
+select -assert-count 1 w:Q a:init=2'b01 %i
+abstract -init w:QQQ
+check -assert
+select -assert-count 1 w:Q a:init=2'b0x %i