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booth cleanup #3938

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merged 11 commits into from
Oct 2, 2023
+497 −730
Merged

booth cleanup #3938

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fedd122
booth: Move away from explicit `Wire` pointers
povik Sep 18, 2023
cb05262
booth: Remove now-unused helpers
povik Sep 19, 2023
986507f
booth: Streamline the low-level circuit emission
povik Sep 19, 2023
30f8387
booth: Rewrite the main cell selection loop
povik Sep 19, 2023
62302f6
booth: Remove more of unused helpers
povik Sep 19, 2023
d641dfa
rtlil: Add helper to emit full-adder cells
povik Sep 19, 2023
cde2a0b
booth: Make more use of appropriate helpers
povik Sep 25, 2023
7179e4f
booth: Improve user interface
povik Sep 25, 2023
91bcf81
booth: Note down debug prints are broken
povik Sep 25, 2023
6b70b3d
booth: Fix assertion
povik Sep 28, 2023
b004530
booth: Cut down the test
povik Sep 28, 2023
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13 changes: 13 additions & 0 deletions kernel/rtlil.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -2677,6 +2677,19 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, const RTLIL::SigSpec &s
return cell;
}

RTLIL::Cell* RTLIL::Module::addFa(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($fa));
cell->parameters[ID::WIDTH] = sig_a.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::B, sig_b);
cell->setPort(ID::C, sig_c);
cell->setPort(ID::X, sig_x);
cell->setPort(ID::Y, sig_y);
cell->set_src_attribute(src);
return cell;
}

RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, const std::string &src)
{
RTLIL::Cell *cell = addCell(name, ID($slice));
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2 changes: 2 additions & 0 deletions kernel/rtlil.h
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Expand Up @@ -1298,6 +1298,8 @@ struct RTLIL::Module : public RTLIL::AttrObject
RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, const std::string &src = "");

RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, const std::string &src = "");

RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
RTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, const std::string &src = "");
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