Hardware Engineering Project (Simple RISC Computer)
Created by Zuhair Shaikh and Brant Lan Li
ELEC374 - Digital Systems Engineering
Department of Electrical and Computer Engineering
Queen's University, Kingston, ON
Description: The purpose of this project is to design, simulate, implement, and verify a Simple RISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O, using Intel Quartus II design software, ModelSim simulation software and Field-Programmable Gate Array (FPGA) hardware. To be implemented on the Cyclone III chip (EP3C16F484) of the DE0 evaluation board or on the Cyclone V chip (5CEBA4F23C7) of the DE0-CV evaluation board.
MIT License
Copyright (c) 2023 [Zuhair Shaikh and Brant Lan Li]
Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.