Initial commit

LICENSE

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+MIT License
+
+Copyright (c) 2019 Andrii Bilynskyi
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

Makefile

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+#****************************************************************************
+#*
+#*  (C) 2019 Andrii Bilynskyi <[email protected]>
+#*
+#*  This code is licenced under the MIT.
+#*
+#****************************************************************************
+
+
+TOOLCHAIN_PATH := /opt/gcc-arm-none-eabi-8-2018-q4-major
+
+
+CC     := ${TOOLCHAIN_PATH}/bin/arm-none-eabi-gcc
+CXX    := ${TOOLCHAIN_PATH}/bin/arm-none-eabi-g++
+OBJCPY := ${TOOLCHAIN_PATH}/bin/arm-none-eabi-objcopy
+FLASH  := openocd
+
+
+PROJECT ?= stm32-test
+
+
+STM32_PERIPH_CSRC := \
+  ${wildcard stm32-periph/*.c} \
+
+STM32_PERIPH_CXXSRC := \
+  ${wildcard stm32-periph/*.cpp} \
+
+STM32_USER_CSRC := \
+  ${wildcard src/*.c} \
+
+STM32_USER_CXXSRC := \
+  ${wildcard src/*.cpp} \
+
+INCLUDE_PATH := \
+  src \
+  stm32-periph \
+
+LDLIBS := \
+
+LD_SCRIPT := linker/stm32_flash.ld
+
+
+OBJECTS := ${STM32_PERIPH_CSRC:.c=.o} ${STM32_PERIPH_CXXSRC:.cpp=.o} ${STM32_USER_CSRC:.c=.o} ${STM32_USER_CXXSRC:.cpp=.o}
+
+CFLAGS  := -g -O3 
+CFLAGS  += -Wall -std=c99
+CFLAGS  += -mlittle-endian -mthumb -mcpu=cortex-m3
+CFLAGS  += -DSTM32F10X_MD
+CFLAGS  += ${addprefix -I, ${INCLUDE_PATH}}
+
+CXXFLAGS  := -g -O3 
+CXXFLAGS  += -Wall
+CXXFLAGS  += -mlittle-endian -mthumb -mcpu=cortex-m3
+CXXFLAGS  += -DSTM32F10X_MD
+CXXFLAGS  += ${addprefix -I, ${INCLUDE_PATH}}
+
+LDFLAGS := -T${LD_SCRIPT}
+LDFLAGS += -mlittle-endian -mthumb -mcpu=cortex-m3
+LDFLAGS += -Wl,--gc-sections
+LDFLAGS += ${addprefix -l, ${LDLIBS}}
+
+
+FLASHCONFIGS := \
+  openocd/jlink.cfg \
+  openocd/stm32f1x.cfg \
+
+FLASHCOMMANDS := \
+  -c "init" \
+  -c "reset init" \
+  -c "flash write_image erase $(PROJECT).hex" \
+  -c "reset" \
+  -c "shutdown" \
+
+FLASHOPTIONS := ${addprefix -f , ${FLASHCONFIGS}} ${FLASHCOMMANDS}
+
+
+.PHONY: all clean flash help
+
+all: ${PROJECT}.hex
+
+${PROJECT}.hex: ${PROJECT}.elf
+	${OBJCPY} -O ihex ${PROJECT}.elf ${PROJECT}.hex
+
+${PROJECT}.elf: ${OBJECTS}
+	${CC} ${OBJECTS} -o ${PROJECT}.elf ${LDFLAGS}
+
+%.o: %.c
+	${CC} ${CFLAGS} -c $< -o $@
+
+%.o: %.cpp
+	${CC} ${CXXFLAGS} -c $< -o $@
+
+clean:
+	rm -f ${OBJECTS} ${PROJECT}.elf ${PROJECT}.hex
+
+flash: ${PROJECT}.hex
+	${FLASH} ${FLASHOPTIONS}
+
+help:
+	@echo "---------------------------------------------------------------------"
+	@echo "all   - create binary files (.elf, .hex)"
+	@echo "clean - remove generated files"	
+	@echo "flash - flash target"
+	@echo "---------------------------------------------------------------------"

README.md

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+# STM32 development under Linux
+
+## Cheap startup hardware
+
+**USB JTAG Jlink clone** <br/>
+https://ru.aliexpress.com/item/New-JLink-OB-ARM-Emulator-Debugger-Programmer-Downloader-for-Replace-V8-SWD-M74/32827782488.html?spm=a2g0v.10010108.1000014.5.63f67f76c8Ikyq&pvid=de125860-82b2-43f4-a546-0bd2bf70b9c7&gps-id=pcDetailBottomMoreOtherSeller&scm=1007.13338.112235.000000000000000&scm-url=1007.13338.112235.000000000000000&scm_id=1007.13338.112235.000000000000000
+
+**Evaluation STM32 board** <br/>
+https://ru.aliexpress.com/item/STM32F103C8T6-ARM-STM32-arduino/32887666464.html?spm=2114.13010708.0.0.134f33edtKnEcc
+
+## Board description:
+
+https://wiki.stm32duino.com/index.php?title=Blue_Pill#Software_installation
+
+## Flashing tools
+
+https://www.segger.com/downloads/flasher/ <br/>
+Select product for your operation system. In case of Ubuntu 64 bit use: 
+J-Link Software and Documentation pack for Linux, DEB installer, 64-bit.
+To flash/erase use JFlashLiteExe.
+
+## Development tools
+
+**GNU Arm Embedded Toolchain** <br/>
+https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads
+
+**openocd** <br/>
+Available as package in most Linux distros.
+
+## OpenOCD debugging
+
+Start server
+
+    openocd -f openocd/jlink.cfg -f openocd/stm32f1x.cfg
+
+Start client
+
+    <path_to_your_toolchain>/bin/arm-none-eabi-gdb -ex "target remote localhost:3333" <your_generated_elf_file>
+
+Download binary file
+
+    monitor reset halt
+    load
+    monitor reset run
+
+General commands:
+
+| command                              | description                                       |
+|--------------------------------------|---------------------------------------------------|
+| monitor reset halt                   | reset MCU and stop                                |
+| continue                             | run SW (to stop Ctrl+C)                           |
+| next/nexti                           | next codeline/instruction                         |
+| step/stepi                           | next codeline/instruction with entering functions |
+| finish                               | exit from current function                        |
+| until                                | run until reach line greater current (loop exit)  |
+| list/list-                           | show 10 code lines down/up                        |
+| break < function, line, file:line >  | add breakpoint                                    |
+| break *0x< address >                 | add breakpoint on hw address                      |
+| watch < variable >                   | set watchpoint on write to variable               |
+| watch *0x< address >                 | set watchpoint on write to address                |
+| rwatch < variable >                  | set watchpoint on read from variable              |
+| awatch < variable >                  | set watchpoint on read or write variable          |
+| print < variable >                   | show variable                                     |
+| display < variable >                 | add variable to watch list                        |
+| info breakpoints/dispaly             | show breakpoints/watchpoints information          |
+| delete breakpoint/dispaly < id >     | delete breakpoint/watchpoint by id from display   |
+| enable breakpoint/dispaly < id >     | enable breakpoint/watchpoint by id from display   |
+| disable breakpoint/dispaly < id >    | disable breakpoint/watchpoint by id from display  |
+| set < variable >:=< value >          | assign new value to variable                      |
+| info registers                       | show registers                                    |
+| monitor reg                          | add registers to permanent watch                  |
+| backtrace                            | show stack                                        |
+| quit                                 | exit debugger                                     |
+
+## gdb GUI
+
+**ddd** - The Data Display Debugger
+Available as package in most Linux distros.
+
+Start ddd
+
+    ddd <your_generated_elf_file> --debugger "<path_to_your_toolchain>/bin/arm-none-eabi-gdb"
+
+Connect to gdb server (issue command in command window)
+
+    target extended-remote :3333

linker/stm32_flash.ld

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+/*
+*****************************************************************************
+**
+**  (C) 2019 Andrii Bilynskyi <[email protected]>
+**
+**  This code is licenced under the MIT.
+**
+*****************************************************************************
+*/
+
+MEMORY
+{
+    FLASH (rx)      : ORIGIN = 0x08000000, LENGTH = 128K
+    RAM   (rwx)     : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+ENTRY(Reset_Handler)
+
+_estack = 0x20005000;           /* end of 20K RAM */
+
+SECTIONS
+{
+
+    .isr_vector : ALIGN(4)
+    {
+        KEEP(*(.isr_vector))
+    } > FLASH
+
+    .text : ALIGN(4)
+    {
+        *(.text)
+
+        KEEP (*(.init))
+        KEEP (*(.fini))
+
+    } > FLASH
+
+    .data_init : ALIGN(4) 
+    {   
+        _sidata = .;
+        *(.data_init)
+    } > FLASH
+
+    .data : ALIGN(4)
+    {
+        _sdata = .;
+        *(.data)
+        _edata = .;
+    } > RAM AT > FLASH
+
+    .bss : ALIGN(4)
+    {
+        _sbss = .;
+        *(.bss)
+        _ebss = .;
+    } > RAM
+
+}

openocd/jlink.cfg

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+interface jlink
+adapter_khz 12000
+transport select swd

openocd/stm32f1x.cfg

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+# script for stm32f1x family
+
+#
+# stm32 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME stm32f1x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 4kB (as found on some STM32F100s)
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      # See STM Document RM0008 Section 26.6.3
+      set _CPUTAPID 0x3ba00477
+   } {
+      # this is the SW-DP tap id not the jtag tap id
+      set _CPUTAPID 0x1ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# flash size will be probed
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+# JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
+adapter_khz 1000
+
+adapter_nsrst_delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+    # if srst is not fitted use SYSRESETREQ to
+    # perform a soft reset
+    cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event examine-end {
+	# DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
+	#              DBG_STANDBY | DBG_STOP | DBG_SLEEP
+	mmw 0xE0042004 0x00000307 0
+}
+
+$_TARGETNAME configure -event trace-config {
+	# Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+	# change this value accordingly to configure trace pins
+	# assignment
+	mmw 0xE0042004 0x00000020 0
+}