Merge branch 'main' into FEAT__Add_distributed_filters

doc/source/Resources/pyaedt_installer_from_aedt.py

@@ -39,6 +39,20 @@
 
 
 VENV_DIR_PREFIX = ".pyaedt_env"
+
+"""
+It is possible create Python virtual environment in a specific directory by setting variable VENV_DIR. 
+For example,
+VENV_DIR = "e:/pyaedt_env"
+"""
+VENV_DIR = None
+if not VENV_DIR:
+    if is_windows:
+        VENV_DIR = os.path.join(os.environ["APPDATA"], VENV_DIR_PREFIX)
+    else:
+        VENV_DIR = os.path.join(os.environ["HOME"], VENV_DIR_PREFIX)
+
+
 DISCLAIMER = (
     "This script will download and install certain third-party software and/or "
     "open-source software (collectively, 'Third-Party Software'). Such Third-Party "
@@ -99,10 +113,10 @@ def run_pyinstaller_from_c_python(oDesktop):
     # Add PyAEDT tabs in AEDT
     # Virtual environment path and Python executable
     if is_windows:
-        venv_dir = os.path.join(os.environ["APPDATA"], VENV_DIR_PREFIX, python_version_new)
+        venv_dir = os.path.join(VENV_DIR, python_version_new)
         python_exe = os.path.join(venv_dir, "Scripts", "python.exe")
     else:
-        venv_dir = os.path.join(os.environ["HOME"], VENV_DIR_PREFIX, python_version_new)
+        venv_dir = os.path.join(VENV_DIR, python_version_new)
         python_exe = os.path.join(venv_dir, "bin", "python")
     pyaedt_path = os.path.join(venv_dir, "Lib", "site-packages", "ansys", "aedt", "core")
     if is_linux:
@@ -207,11 +221,11 @@ def install_pyaedt():
         python_version = "3_7"
 
     if is_windows:
-        venv_dir = Path(os.environ["APPDATA"], VENV_DIR_PREFIX, python_version)
+        venv_dir = Path(VENV_DIR, python_version)
         python_exe = venv_dir / "Scripts" / "python.exe"
         pip_exe = venv_dir / "Scripts" / "pip.exe"
     else:
-        venv_dir = Path(os.environ["HOME"], VENV_DIR_PREFIX, python_version)
+        venv_dir = Path(VENV_DIR, python_version)
         python_exe = venv_dir / "bin" / "python"
         pip_exe = venv_dir / "bin" / "pip"
         os.environ["ANSYSEM_ROOT{}".format(args.version)] = args.edt_root

src/ansys/aedt/core/application/aedt_objects.py

@@ -81,6 +81,7 @@ def __init__(self, desktop=None, project=None, design=None, is_inherithed=False)
         self._o_symbol_manager = None
         self._opadstackmanager = None
         self._oradfield = None
+        self._onetwork_data_explorer = None
 
     @property
     def oradfield(self):
@@ -429,3 +430,15 @@ def o_model_manager(self):
         if not self._o_model_manager and self.odefinition_manager:
             self._o_model_manager = self.odefinition_manager.GetManager("Model")
         return self._o_model_manager
+
+    @property
+    def onetwork_data_explorer(self):
+        """Network data explorer module.
+
+        References
+        ----------
+        >>> oDesktop.GetTool("NdExplorer")
+        """
+        if not self._onetwork_data_explorer:
+            self._onetwork_data_explorer = self._odesktop.GetTool("NdExplorer")
+        return self._onetwork_data_explorer

src/ansys/aedt/core/circuit.py

@@ -192,7 +192,6 @@ def __init__(
             remove_lock=remove_lock,
         )
         ScatteringMethods.__init__(self, self)
-        self.onetwork_data_explorer = self._desktop.GetTool("NdExplorer")
 
     def _init_from_design(self, *args, **kwargs):
         self.__init__(*args, **kwargs)

src/ansys/aedt/core/desktop.py

@@ -516,8 +516,8 @@ def __init__(
         if getattr(self, "_initialized", None) is not None and self._initialized:
             try:
                 self.grpc_plugin.recreate_application(True)
-            except Exception:  # nosec
-                pass
+            except Exception:
+                pyaedt_logger.debug("Failed to recreate application.")
             return
         else:
             self._initialized = True

src/ansys/aedt/core/generic/general_methods.py

@@ -404,7 +404,7 @@ def open_file(file_path, file_options="r", encoding=None, override_existing=True
 
     Parameters
     ----------
-    file_path : str
+    file_path : str or Path
         Full absolute path to the file (either local or remote).
     file_options : str, optional
         Options for opening the file.

src/ansys/aedt/core/hfss.py

@@ -232,7 +232,6 @@ def __init__(
             remove_lock=remove_lock,
         )
         ScatteringMethods.__init__(self, self)
-        self.onetwork_data_explorer = self.odesktop.GetTool("NdExplorer")
         self._field_setups = []
         self.component_array = {}
         self.component_array_names = list(self.get_oo_name(self.odesign, "Model"))

src/ansys/aedt/core/hfss3dlayout.py

@@ -187,7 +187,6 @@ def __init__(
             remove_lock=remove_lock,
         )
         ScatteringMethods.__init__(self, self)
-        self.onetwork_data_explorer = self.odesktop.GetTool("NdExplorer")
 
     def _init_from_design(self, *args, **kwargs):
         self.__init__(*args, **kwargs)

src/ansys/aedt/core/modeler/circuits/primitives_nexxim.py

@@ -22,7 +22,7 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-import os
+from pathlib import Path
 import re
 import secrets
 import time
@@ -314,8 +314,9 @@ def connect_components_in_series(self, assignment, use_wire=True):
                     if component in [cmp.id, cmp.name, cmp.composed_name]:
                         comps.append(cmp)
                         break
+        if len(comps) < 2:
+            raise RuntimeError("At least two components have to be passed.")
         i = 0
-        assert len(comps) > 1, "At least two components have to be passed."
         while i < (len(comps) - 1):
             comps[i].pins[-1].connect_to_component(comps[i + 1].pins[0], use_wire=use_wire)
             i += 1
@@ -352,7 +353,8 @@ def connect_components_in_parallel(self, assignment):
                     if component in [cmp.id, cmp.name, cmp.composed_name]:
                         comps.append(cmp)
                         break
-        assert len(comps) > 1, "At least two components have to be passed."
+        if len(comps) < 2:
+            raise RuntimeError("At least two components have to be passed.")
         comps[0].pins[0].connect_to_component([i.pins[0] for i in comps[1:]])
         terminal_to_connect = [cmp for cmp in comps if len(cmp.pins) >= 2]
         if len(terminal_to_connect) > 1:
@@ -1616,14 +1618,14 @@ def _add_subcircuit_link(
             Name of the subcircuit HFSS link.
         pin_names : list
             List of the pin names.
-        source_project_path : str
+        source_project_path : str or Path
             Path to the source project.
         source_design_name : str
             Name of the design.
         solution_name : str, optional
             Name of the solution and sweep. The
             default is ``"Setup1 : Sweep"``.
-        image_subcircuit_path : str, optional
+        image_subcircuit_path : str or Path or None
             Path of the Picture used in Circuit.
             Default is an HFSS Picture exported automatically.
         model_type : str, optional
@@ -1647,6 +1649,8 @@ def _add_subcircuit_link(
         >>> oComponentManager.Add
         >>> oDesign.AddCompInstance
         """
+        if isinstance(source_project_path, str):
+            source_project_path = Path(source_project_path)
         model = "hfss"
         owner = "HFSS"
         icon_file = "hfss.bmp"
@@ -1668,19 +1672,20 @@ def _add_subcircuit_link(
         hspice_customization = self._get_comp_custom_settings(3, 1, 2, 3, 0, 0, "False", "", 3)
 
         if image_subcircuit_path:
-            _, file_extension = os.path.splitext(image_subcircuit_path)
-            if file_extension != ".gif" or file_extension != ".bmp" or file_extension != ".jpg":
+            if isinstance(image_subcircuit_path, str):
+                image_subcircuit_path = Path(image_subcircuit_path)
+            if image_subcircuit_path.suffix not in [".gif", ".bmp", ".jpg"]:
                 image_subcircuit_path = None
                 warnings.warn("Image extension is not valid. Use default image instead.")
         if not image_subcircuit_path:
-            image_subcircuit_path = os.path.normpath(
-                os.path.join(self._modeler._app.desktop_install_dir, "syslib", "Bitmaps", icon_file)
-            )
+            image_subcircuit_path = (
+                Path(self._modeler._app.desktop_install_dir) / "syslib" / "Bitmaps" / icon_file
+            ).resolve()
         filename = ""
         comp_name_aux = generate_unique_name(source_design_name)
         WB_SystemID = source_design_name
-        if not self._app.project_file == source_project_path:
-            filename = source_project_path
+        if Path(self._app.project_file) != source_project_path:
+            filename = str(source_project_path)
             comp_name_aux = comp_name
             WB_SystemID = ""
 
@@ -1699,7 +1704,7 @@ def _add_subcircuit_link(
             "Description:=",
             "",
             "ImageFile:=",
-            image_subcircuit_path,
+            str(image_subcircuit_path),
             "SymbolPinConfiguration:=",
             0,
             ["NAME:PortInfoBlk"],
@@ -1946,7 +1951,7 @@ def set_sim_solution_on_hfss_subcircuit(self, component, solution_name="Setup1 :
 
     @pyaedt_function_handler()
     def _edit_link_definition_hfss_subcircuit(self, component, edited_prop):
-        """Generic function to set the link definition for an hfss subcircuit."""
+        """Generic function to set the link definition for a HFSS subcircuit."""
         if isinstance(component, str):
             complist = component.split(";")
         elif isinstance(component, CircuitComponent):
@@ -1955,16 +1960,21 @@ def _edit_link_definition_hfss_subcircuit(self, component, edited_prop):
             complist = self.components[component].composed_name.split(";")
         else:
             raise AttributeError("Wrong Component Input")
-        complist2 = complist[0].split("@")
-        arg = ["NAME:AllTabs"]
-        arg1 = ["NAME:Model"]
-        arg2 = ["NAME:PropServers", "Component@" + str(complist2[1])]
-        arg3 = ["NAME:ChangedProps", edited_prop]
-
-        arg1.append(arg2)
-        arg1.append(arg3)
-        arg.append(arg1)
 
+        arg = [
+            "NAME:AllTabs",
+            [
+                "NAME:Model",
+                [
+                    "NAME:PropServers",
+                    "Component@" + str(complist[0].split("@")[1]),
+                ],
+                [
+                    "NAME:ChangedProps",
+                    edited_prop,
+                ],
+            ],
+        ]
         self._app._oproject.ChangeProperty(arg)
         return True
 
@@ -2016,7 +2026,7 @@ def create_component_from_spicemodel(
 
         Parameters
         ----------
-        input_file : str
+        input_file : str or Path
             Path to .lib file.
         model : str, optional
             Model name to import. If `None` the first subckt in the lib file will be placed.
@@ -2038,12 +2048,15 @@ def create_component_from_spicemodel(
 
         Examples
         --------
+        >>> from pathlib import Path
         >>> from ansys.aedt.core import Circuit
         >>> cir = Circuit(version="2023.2")
-        >>> model = os.path.join("Your path", "test.lib")
+        >>> model = Path("Your path") / "test.lib"
         >>> cir.modeler.schematic.create_component_from_spicemodel(input_file=model,model="GRM1234",symbol="nexx_cap")
         >>> cir.release_desktop(False, False)
         """
+        if isinstance(input_file, str):
+            input_file = Path(input_file)
         models = self._parse_spice_model(input_file)
         if not model and models:
             model = models[0]
@@ -2061,20 +2074,19 @@ def create_component_from_spicemodel(
             else:
                 arg2.append([False, "", "", False])
         arg.append(arg2)
-        self.o_component_manager.ImportModelsFromFile(input_file.replace("\\", "/"), arg)
+        self.o_component_manager.ImportModelsFromFile(input_file.as_posix(), arg)
 
         if create_component:
             return self.create_component(None, component_library=None, component_name=model, location=location)
-        else:
-            return True
+        return True
 
     @pyaedt_function_handler(model_path="input_file", solution_name="solution")
     def add_siwave_dynamic_link(self, input_file, solution=None, simulate_solutions=False):
         """Add a siwave dinamyc link object.
 
         Parameters
         ----------
-        input_file : str
+        input_file : str or Path
             Full path to the .siw file.
         solution : str, optional
             Solution name.
@@ -2086,18 +2098,20 @@ def add_siwave_dynamic_link(self, input_file, solution=None, simulate_solutions=
         :class:`ansys.aedt.core.modeler.circuits.object_3d_circuit.CircuitComponent`
             Circuit Component Object.
         """
-        assert os.path.exists(input_file), "Project file doesn't exist"
-        comp_name = os.path.splitext(os.path.basename(input_file))[0]
-        results_path = input_file + "averesults"
-        solution_path = os.path.join(results_path, comp_name + ".asol")
-        # out = load_entire_aedt_file(solution)
+        if isinstance(input_file, str):
+            input_file = Path(input_file)
+        if not input_file.exists():
+            raise FileNotFoundError(f"Project file '{input_file}' doesn't exist")
+        comp_name = Path(input_file).stem
+        results_path = input_file.parent / f"{comp_name}.siwaveresults"
+        solution_path = results_path / f"{comp_name}.asol"
         out = load_keyword_in_aedt_file(solution_path, "Solutions")
         if not solution:
             solution = list(out["Solutions"]["SYZSolutions"].keys())[0]
-        results_folder = os.path.join(
-            results_path,
-            out["Solutions"]["SYZSolutions"][solution]["DiskName"],
-            out["Solutions"]["SYZSolutions"][solution]["DiskName"] + ".syzinfo",
+        results_folder = (
+            results_path
+            / out["Solutions"]["SYZSolutions"][solution]["DiskName"]
+            / f"{out['Solutions']['SYZSolutions'][solution]['DiskName']}.syzinfo"
         )
 
         pin_names = []

src/ansys/aedt/core/modeler/geometry_operators.py

@@ -1535,9 +1535,8 @@ def v_angle_sign(va, vb, vn, right_handed=True):
         cross = GeometryOperators.v_cross(va, vb)
         if GeometryOperators.v_norm(cross) < tol:
             return math.pi
-        assert GeometryOperators.is_collinear(cross, vn), (
-            "vn must be the normal to the " "plane containing va and vb."
-        )  # pragma: no cover
+        if not GeometryOperators.is_collinear(cross, vn):
+            raise ValueError("vn must be the normal to the plane containing va and vb")  # pragma: no cover
 
         vnn = GeometryOperators.normalize_vector(vn)
         if right_handed:
@@ -1762,10 +1761,11 @@ def is_segment_intersecting_polygon(a, b, polygon):
         float
             ``True`` if the segment intersect the polygon. ``False`` otherwise.
         """
-        assert len(a) == 2, "point must be a list in the form [x, y]"
-        assert len(b) == 2, "point must be a list in the form [x, y]"
+        if len(a) != 2 or len(b) != 2:
+            raise ValueError("Point must be a list in the form [x, y]")
         pl = len(polygon[0])
-        assert len(polygon[1]) == pl, "Polygon x and y lists must be the same length"
+        if len(polygon[1]) != pl:
+            raise ValueError("The two sublists in polygon must have the same length")
 
         a_in = GeometryOperators.is_point_in_polygon(a, polygon)
         b_in = GeometryOperators.is_point_in_polygon(b, polygon)