FEAT: Filtersolutions Export Modelithics (#5101)

Co-authored-by: pre-commit-ci[bot] <66853113+pre-commit-ci[bot]@users.noreply.github.com>

_unittest/test_45_FilterSolutions/resources/__init__.py

@@ -23,3 +23,4 @@
 # SOFTWARE.
 
 from .resources import read_resource_file
+from .resources import resource_path

_unittest/test_45_FilterSolutions/resources/import_tuned_variables.ckt

@@ -0,0 +1,17 @@
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+R0 1 2 50
+C1 2 0 2.296E-12
+L2 2 3 1.688E-08
+C3 3 0 4.517E-12
+L4 3 4 1.688E-08
+C5 4 0 2.296E-12
+R6 4 0 50
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(4) -90 0
+.PLOT AC VP(4) -200 200
+.PLOT AC VG(4) 0 1.2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(4) 0 0.6
+.END

_unittest/test_45_FilterSolutions/resources/imported_netlist.ckt

@@ -0,0 +1,17 @@
+*
+V1 1 0 AC 1 PULSE 0 1 0 1.592E-13 0
+R0 1 2 50
+C1 2 0 2.296E-12
+L2 2 3 1.688E-08
+C3 3 0 4.517E-12
+L4 3 4 1.688E-08
+C5 4 0 2.296E-12
+R6 4 0 50
+*
+.AC DEC 200 2E+08 5E+09
+.PLOT AC VDB(4) -90 0
+.PLOT AC VP(4) -200 200
+.PLOT AC VG(4) 0 1.2E-09
+.TRAN  5E-11 1E-08 0
+.PLOT TRAN V(4) 0 0.6
+.END

_unittest/test_45_FilterSolutions/resources/library_parts.cfg

@@ -0,0 +1,45 @@
+modsubType=2
+modsubEr=4.5
+modsubRho=5.8E+07
+modsubTand=0.035
+modsubH=0.002
+modsubT=5E-07
+modsubS=0.00127
+modsubC=0.00635
+modsubErsel=-1
+modsubRhosel=-1
+modsubTandsel=-1
+modsubTanddef=0
+modsubiSubSel=0
+modsubName=User Defined Substrate
+modsubBrow=
+modsubNameVal=4.5
+modAnsSubIndex=0
+modAWRSubIndex=0
+webAWRSubIndex=0
+locAWRSubIndex=0
+ModelData=2
+ModelDataV=1
+ModelInd=0
+ModelCap=3
+ModelRes=0
+ModelIndV=1
+ModelCapV=1
+ModelResV=1
+modRatLen=2
+modRatZ=1
+Interc=1
+modActLen=0.00254
+modActWid=0.00127
+modRatZMin=0.5
+modRatZMax=2
+modRatLenMin=0.5
+modRatLenMax=2
+modActLenMin=0.00127
+modActWidMin=0.000635
+modActLenMax=0.00508
+modActWidMax=0.00254
+useGeo=0
+OptGeo=1
+indTol=1
+capTol=1

_unittest/test_45_FilterSolutions/test_lumped_export/__init__.py

@@ -0,0 +1,23 @@
+# -*- coding: utf-8 -*-
+#
+# Copyright (C) 2021 - 2024 ANSYS, Inc. and/or its affiliates.
+# SPDX-License-Identifier: MIT
+#
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in all
+# copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.

_unittest/test_45_FilterSolutions/test_lumped_export/test_optimization_goals_table.py

@@ -37,13 +37,13 @@ class TestClass:
     def test_row_count(self):
         lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)
         lumpdesign.export_to_aedt._open_aedt_export()
-        lumpdesign.optimization_goals_table.set_design_goals()
+        lumpdesign.optimization_goals_table.restore_design_goals()
         assert lumpdesign.optimization_goals_table.row_count == 2
 
     def test_row(self):
         lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)
         lumpdesign.export_to_aedt._open_aedt_export()
-        lumpdesign.optimization_goals_table.set_design_goals()
+        lumpdesign.optimization_goals_table.restore_design_goals()
         assert lumpdesign.optimization_goals_table.row(0) == [
             "200 MHz",
             "1 GHz",
@@ -71,7 +71,7 @@ def test_row(self):
     def test_update_row(self):
         lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)
         lumpdesign.export_to_aedt._open_aedt_export()
-        lumpdesign.optimization_goals_table.set_design_goals()
+        lumpdesign.optimization_goals_table.restore_design_goals()
         lumpdesign.optimization_goals_table.update_row(
             0, lower_frequency="100 MHz", upper_frequency="2 GHz", condition=">", weight="0.7"
         )
@@ -88,7 +88,7 @@ def test_update_row(self):
     def test_append_row(self):
         lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)
         lumpdesign.export_to_aedt._open_aedt_export()
-        lumpdesign.optimization_goals_table.set_design_goals()
+        lumpdesign.optimization_goals_table.restore_design_goals()
         lumpdesign.optimization_goals_table.append_row("100 MHz", "2 GHz", "-3", ">", "dB(S(Port2,Port2))", "0.3", "Y")
         assert lumpdesign.optimization_goals_table.row(2) == [
             "100 MHz",
@@ -103,7 +103,7 @@ def test_append_row(self):
     def test_insert_row(self):
         lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)
         lumpdesign.export_to_aedt._open_aedt_export()
-        lumpdesign.optimization_goals_table.set_design_goals()
+        lumpdesign.optimization_goals_table.restore_design_goals()
         lumpdesign.optimization_goals_table.insert_row(
             1, "100 MHz", "2 GHz", "-3", ">", "dB(S(Port2,Port2))", "0.3", "Y"
         )
@@ -120,7 +120,7 @@ def test_insert_row(self):
     def test_remove_row(self):
         lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)
         lumpdesign.export_to_aedt._open_aedt_export()
-        lumpdesign.optimization_goals_table.set_design_goals()
+        lumpdesign.optimization_goals_table.restore_design_goals()
         lumpdesign.optimization_goals_table.remove_row(1)
         assert lumpdesign.optimization_goals_table.row_count == 1
         assert lumpdesign.optimization_goals_table.row(0) == [
@@ -136,7 +136,7 @@ def test_remove_row(self):
     def test_adjust_goal_frequency(self):
         lumpdesign = ansys.aedt.core.FilterSolutions(implementation_type=FilterImplementation.LUMPED)
         lumpdesign.export_to_aedt._open_aedt_export()
-        lumpdesign.optimization_goals_table.set_design_goals()
+        lumpdesign.optimization_goals_table.restore_design_goals()
         lumpdesign.optimization_goals_table.adjust_goal_frequency("150 MHz")
         assert lumpdesign.optimization_goals_table.row(0)[OptimizationGoalParameter.LOWER_FREQUENCY.value] == "350 MHz"
         assert lumpdesign.optimization_goals_table.row(0)[OptimizationGoalParameter.UPPER_FREQUENCY.value] == "1.15 GHz"

examples/08-FilterSolutions/Lumped_Element_Response.py

@@ -14,14 +14,14 @@
 import ansys.aedt.core.filtersolutions_core.attributes
 from ansys.aedt.core.filtersolutions_core.attributes import FilterType, FilterClass, FilterImplementation
 from ansys.aedt.core.filtersolutions_core.ideal_response import FrequencyResponseColumn
+from ansys.aedt.core.filtersolutions_core.export_to_aedt import PartLibraries, ExportFormat
 import matplotlib.pyplot as plt
 
 ###############################################################################
 # Create the lumped design
 # ~~~~~~~~~~~~~~~~~~~~~~~~
 # Create a lumped element filter design and assign the class, type, frequency, and order.
-design = ansys.aedt.core.FilterSolutions(version="2025.1", implementation_type= FilterImplementation.LUMPED)   
-
+design = ansys.aedt.core.FilterSolutions(version="2025.1", implementation_type= FilterImplementation.LUMPED) 
 design.attributes.filter_class = FilterClass.BAND_PASS
 design.attributes.filter_type = FilterType.BUTTERWORTH
 design.attributes.pass_band_center_frequency = "1G"