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Create SYZ project (SimulationConfiguration) | ||
=========================================== | ||
This section describes how to create SYZ simulation setup for Siwave using SimulationConfiguration class. | ||
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.. autosummary:: | ||
:toctree: _autosummary | ||
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.. code:: python | ||
from pyedb.legacy.edb_core.edb import EdbLegacy | ||
from pyedb.generic.constants import SolverType | ||
# Ansys release version | ||
ansys_version = "2023.2" | ||
#download and copy the layout file from examples | ||
from pyedb.legacy.edb import EdbLegacy | ||
from pyedb.generic.general_methods import generate_unique_folder_name | ||
import pyedb.misc.downloads as downloads | ||
temp_folder = generate_unique_folder_name() | ||
targetfile = downloads.download_file('edb/Powerboard_SiC_MOSFET.tgz', destination=temp_folder) | ||
# loading EDB | ||
edbapp = EdbLegacy(edbpath=targetfile, edbversion="2023.2") | ||
simconfig = edbapp.new_simulation_configuration() | ||
simconfig.solver_type = SolverType.SiwaveSYZ | ||
simconfig.mesh_freq = "40.25GHz" | ||
edbapp.build_simulation_project(simconfig) | ||
edbapp.close() |
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Create coaxial port on component | ||
================================ | ||
This section shows a simple example to create HFSS coaxial port on a component. | ||
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.. autosummary:: | ||
:toctree: _autosummary | ||
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.. code:: python | ||
from pyedb.legacy.edb_core.edb import EdbLegacy | ||
# Ansys release version | ||
ansys_version = "2023.2" | ||
#download and copy the layout file from examples | ||
from pyedb.legacy.edb import EdbLegacy | ||
from pyedb.generic.general_methods import generate_unique_folder_name | ||
import pyedb.misc.downloads as downloads | ||
temp_folder = generate_unique_folder_name() | ||
targetfile = downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
# loading EDB | ||
edbapp = EdbLegacy(edbpath=targetfile, edbversion="2023.2") | ||
sim_setup = edbapp.new_simulation_configuration() | ||
sim_setup.signal_nets = [ | ||
"DDR4_A0", | ||
"DDR4_A1", | ||
"DDR4_A2", | ||
"DDR4_A3", | ||
"DDR4_A4", | ||
"DDR4_A5", | ||
] | ||
sim_setup.power_nets = ["GND"] | ||
sim_setup.do_cutout_subdesign = True | ||
sim_setup.components = ["U1", "U15"] | ||
sim_setup.use_default_coax_port_radial_extension = False | ||
sim_setup.cutout_subdesign_expansion = 0.001 | ||
sim_setup.start_freq = 0 | ||
sim_setup.stop_freq = 20e9 | ||
sim_setup.step_freq = 10e6 | ||
edbapp.build_simulation_project(sim_setup) | ||
edbapp.close() |
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Create AC simulation setup | ||
========================== | ||
This section describes how to create AC simulation setup for Siwave. | ||
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.. autosummary:: | ||
:toctree: _autosummary | ||
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.. code:: python | ||
from pyedb.legacy.edb_core.edb import EdbLegacy | ||
from pyedb.generic.constants import SolverType | ||
# Ansys release version | ||
ansys_version = "2023.2" | ||
#download and copy the layout file from examples | ||
from pyedb.legacy.edb import EdbLegacy | ||
from pyedb.generic.general_methods import generate_unique_folder_name | ||
import pyedb.misc.downloads as downloads | ||
temp_folder = generate_unique_folder_name() | ||
targetfile = downloads.download_file('edb/Powerboard_SiC_MOSFET.tgz', destination=temp_folder) | ||
# loading EDB | ||
edbapp = EdbLegacy(edbpath=targetfile, edbversion="2023.2") | ||
# create AC simulation setup | ||
setup1 = edbapp.create_siwave_syz_setup("AC1") | ||
setup1.advanced_settings.restore_default() | ||
# get configuration defaults settings | ||
settings = edbapp.setups["AC1"].get_configurations() | ||
for k, v in setup1.advanced_settings.defaults.items(): | ||
if k in ["min_plane_area_to_mesh"]: | ||
continue | ||
settings["advanced_settings"][k] == v | ||
# SI settings | ||
for p in [0, 1, 2]: | ||
setup1.set_si_slider(p) | ||
settings = edbapp.setups["AC1"].get_configurations() | ||
for k, v in setup1.advanced_settings.si_defaults.items(): | ||
settings["advanced_settings"][k] == v[p] | ||
# PI settings | ||
for p in [0, 1, 2]: | ||
setup1.set_pi_slider(p) | ||
settings = edbapp.setups["AC1"].get_configurations() | ||
for k, v in setup1.advanced_settings.pi_defaults.items(): | ||
settings["advanced_settings"][k] == v[p] | ||
# add frequency sweep | ||
sweep = setup1.add_frequency_sweep( | ||
"sweep1", | ||
frequency_sweep=[ | ||
["linear count", "0", "1kHz", 1], | ||
["log scale", "1kHz", "0.1GHz", 10], | ||
["linear scale", "0.1GHz", "10GHz", "0.1GHz"], | ||
], | ||
) | ||
# settings sweep options | ||
sweep.adaptive_sampling = True | ||
sweep.adv_dc_extrapolation = True | ||
sweep.compute_dc_point = True | ||
sweep.auto_s_mat_only_solve = False | ||
sweep.enforce_causality = True | ||
sweep.enforce_dc_and_causality = True | ||
sweep.enforce_passivity = False | ||
sweep.freq_sweep_type = "kDiscreteSweep" | ||
sweep.interpolation_use_full_basis = False | ||
sweep.interpolation_use_port_impedance = False | ||
sweep.interpolation_use_prop_const = False | ||
sweep.max_solutions = 200 | ||
sweep.min_freq_s_mat_only_solve = "2MHz" | ||
sweep.min_solved_freq = "1Hz" | ||
sweep.passivity_tolerance = 0.0002 | ||
sweep.relative_s_error = 0.004 | ||
sweep.save_fields = True | ||
sweep.save_rad_fields_only = True | ||
sweep.use_q3d_for_dc = True |
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Create EDB with DXF file | ||
======================== | ||
This section describes how to create EDB from DXF file. | ||
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.. autosummary:: | ||
:toctree: _autosummary | ||
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.. code:: python | ||
from pyedb.legacy.edb_core.edb import EdbLegacy | ||
dxf_path = os.path.join(local_path, "edb_test.dxf") | ||
edb = EdbLegacy(dxf_path, edbversion="2023.2") | ||
edb.close() |
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Create pad-stack instance | ||
========================= | ||
This section describes how create padsatck instance. | ||
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.. autosummary:: | ||
:toctree: _autosummary | ||
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.. code:: python | ||
from pyedb.legacy.edb_core.edb import EdbLegacy | ||
edb = EdbLegacy(edbversion=desktop_version) | ||
edb.stackup.add_layer(layer_name="1_Top", fillMaterial="AIR", thickness="30um") | ||
edb.stackup.add_layer(layer_name="contact", fillMaterial="AIR", thickness="100um", base_layer="1_Top") | ||
edb.padstacks.create( | ||
pad_shape="Rectangle", | ||
padstackname="pad", | ||
x_size="350um", | ||
y_size="500um", | ||
holediam=0, | ||
) | ||
pad_instance1 = edb.padstacks.place(position=["-0.65mm", "-0.665mm"], definition_name="pad") | ||
pad_instance1.start_layer = "1_Top" | ||
pad_instance1.stop_layer = "1_Top" | ||
edb.padstacks.create(pad_shape="Circle", padstackname="pad2", paddiam="350um", holediam="15um") | ||
pad_instance2 = edb.padstacks.place(position=["-0.65mm", "-0.665mm"], definition_name="pad2") | ||
pad_instance2.start_layer = "1_Top" | ||
pad_instance2.stop_layer = "1_Top" | ||
edb.padstacks.create( | ||
pad_shape="Circle", | ||
padstackname="test2", | ||
paddiam="400um", | ||
holediam="200um", | ||
antipad_shape="Rectangle", | ||
anti_pad_x_size="700um", | ||
anti_pad_y_size="800um", | ||
start_layer="1_Top", | ||
stop_layer="1_Top", | ||
) | ||
pad_instance3 = edb.padstacks.place(position=["-1.65mm", "-1.665mm"], definition_name="test2") | ||
pad_instance3.dcir_equipotential_region = True | ||
pad_instance3.dcir_equipotential_region = False | ||
trace = edb.modeler.create_trace([[0, 0], [0, 10e-3]], "1_Top", "0.1mm", "trace_with_via_fence") | ||
edb.padstacks.create_padstack("via_0") | ||
trace.create_via_fence("1mm", "1mm", "via_0") | ||
edb.close() |
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doc/source/User_guide/create_port_between_pin_and_layer.rst
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Create port between pin and layer | ||
================================= | ||
This section describes how create port between pin and layer. | ||
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.. autosummary:: | ||
:toctree: _autosummary | ||
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.. code:: python | ||
from pyedb.legacy.edb_core.edb import EdbLegacy | ||
# Ansys release version | ||
ansys_version = "2023.2" | ||
#download and copy the layout file from examples | ||
from pyedb.legacy.edb import EdbLegacy | ||
from pyedb.generic.general_methods import generate_unique_folder_name | ||
import pyedb.misc.downloads as downloads | ||
temp_folder = generate_unique_folder_name() | ||
targetfile = downloads.download_file('edb/ANSYS-HSD_V1.aedb', destination=temp_folder) | ||
# loading EDB | ||
edbapp = EdbLegacy(edbpath=targetfile, edbversion="2023.2") | ||
edbapp.siwave.create_port_between_pin_and_layer( | ||
component_name="U1", pins_name="A27", layer_name="16_Bottom", reference_net="GND" | ||
) | ||
U7 = edbapp.components["U7"] | ||
U7.pins["G7"].create_port() | ||
port = U7.pins["F7"].create_port(reference=U7.pins["E7"]) | ||
port.is_circuit_port = True | ||
_, pin_group = edbapp.siwave.create_pin_group_on_net( | ||
reference_designator="U7", net_name="GND", group_name="U7_GND" | ||
) | ||
U7.pins["F7"].create_port(reference=pin_group) | ||
edbapp.close() |
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Define HFSS extent (SimulationConfiguration) | ||
============================================ | ||
This section describes how define HFSS extent using SimulationConfiguration class. | ||
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.. autosummary:: | ||
:toctree: _autosummary | ||
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.. code:: python | ||
from pyedb.legacy.edb_core.edb import EdbLegacy | ||
# create new EDB | ||
edb = EdbLegacy() | ||
# adding stackup layers | ||
edb.stackup.add_layer(layer_name="GND", fillMaterial="AIR", thickness="30um") | ||
edb.stackup.add_layer(layer_name="FR4", base_layer="gnd", thickness="250um") | ||
edb.stackup.add_layer(layer_name="SIGNAL", base_layer="FR4", thickness="30um") | ||
# create trace | ||
edb.modeler.create_trace(layer_name="SIGNAL", width=0.02, net_name="net1", path_list=[[-1e3, 0, 1e-3, 0]]) | ||
# create primitive rectangle | ||
edb.modeler.create_rectangle( | ||
layer_name="GND", | ||
representation_type="CenterWidthHeight", | ||
center_point=["0mm", "0mm"], | ||
width="4mm", | ||
height="4mm", | ||
net_name="GND", | ||
) | ||
# create SimulationConfiguration object | ||
sim_setup = edb.new_simulation_configuration() | ||
# assign nets | ||
sim_setup.signal_nets = ["net1"] | ||
sim_setup.power_nets = ["GND"] | ||
# define air box settings | ||
sim_setup.use_dielectric_extent_multiple = False | ||
sim_setup.use_airbox_horizontal_extent_multiple = False | ||
sim_setup.use_airbox_negative_vertical_extent_multiple = False | ||
sim_setup.use_airbox_positive_vertical_extent_multiple = False | ||
sim_setup.dielectric_extent = 0.0005 | ||
sim_setup.airbox_horizontal_extent = 0.001 | ||
sim_setup.airbox_negative_vertical_extent = 0.05 | ||
sim_setup.airbox_positive_vertical_extent = 0.04 | ||
# disable frequencvy sweep creation | ||
sim_setup.add_frequency_sweep = False | ||
# include only selected nets | ||
sim_setup.include_only_selected_nets = True | ||
# disable cutout | ||
sim_setup.do_cutout_subdesign = False | ||
# disbale port generation | ||
sim_setup.generate_excitations = False | ||
# build project | ||
edb.build_simulation_project(sim_setup) | ||
edb.close() |
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Define layer stackup | ||
==================== | ||
This section describes how create layer stackup. | ||
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.. autosummary:: | ||
:toctree: _autosummary | ||
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.. code:: python | ||
from pyedb.legacy.edb_core.edb import EdbLegacy | ||
edb = EdbLegacy(edbversion=desktop_version) | ||
edb.stackup.add_layer(layer_name="gnd", fillMaterial="AIR", thickness="10um") | ||
edb.stackup.add_layer(layer_name="diel1", fillMaterial="AIR", thickness="200um", base_layer="gnd") | ||
edb.stackup.add_layer(layer_name="sig1", fillMaterial="AIR", thickness="10um", base_layer="diel1") | ||
edb.stackup.add_layer(layer_name="diel2", fillMaterial="AIR", thickness="200um", base_layer="sig1") | ||
edb.stackup.add_layer(layer_name="sig3", fillMaterial="AIR", thickness="10um", base_layer="diel2") | ||
edb.close() |
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Delete pin group | ||
================ | ||
This section describes how to delete pin group. | ||
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.. autosummary:: | ||
:toctree: _autosummary | ||
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.. code:: python | ||
from pyedb.legacy.edb_core.edb import EdbLegacy | ||
# loading EDB | ||
edbapp = EdbLegacy(edbpath=targetfile, edbversion="2023.2") | ||
for _, pingroup in edbapp.siwave.pin_groups.items(): | ||
ingroup.delete() | ||
edbapp.close() |
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