FIX: add name

ansys · May 23, 2024 · e411546 · e411546
1 parent 168ac53
commit e411546
Showing 1 changed file with 10 additions and 0 deletions.
diff --git a/tests/legacy/system/test_edb.py b/tests/legacy/system/test_edb.py
@@ -1184,6 +1184,16 @@ def test_siwave_create_port_between_pin_and_layer(self):
         ]
         for term in padstack_instance_terminals:
             assert term.position
+        pos_pin = edbapp.padstacks.get_pinlist_from_component_and_net("C173")[1]
+        neg_pin = edbapp.padstacks.get_pinlist_from_component_and_net("C172")[0]
+        edbapp.create_port(
+            pos_pin.get_terminal(create_new_terminal=True),
+            neg_pin.get_terminal(create_new_terminal=True),
+            is_circuit_port=True,
+            name="test",
+        )
+        assert edbapp.ports["test"]
+        assert edbapp.ports["test"].is_circuit_port == True
         edbapp.close()
 
     def test_siwave_source_setter(self):