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Considering powerPc architecture in all tests
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@bohlender
bohlender committed Dec 24, 2018
1 parent 4da9c21 commit bcb0123
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Showing 7 changed files with 97 additions and 2 deletions.
4 changes: 3 additions & 1 deletion source/capstone/api.d
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Expand Up @@ -334,13 +334,15 @@ abstract class Capstone{
modeFlags = The mode of interpretation
*/
static Capstone create(Arch arch, ModeFlags modeFlags){
switch(arch){
switch(arch){ // TODO: final switch
case Arch.arm:
return new CapstoneImpl!(Arch.arm)(modeFlags);
case Arch.arm64:
return new CapstoneImpl!(Arch.arm64)(modeFlags);
case Arch.mips:
return new CapstoneImpl!(Arch.mips)(modeFlags);
case Arch.ppc:
return new CapstoneImpl!(Arch.ppc)(modeFlags);
case Arch.x86:
return new CapstoneImpl!(Arch.x86)(modeFlags);
default:
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2 changes: 2 additions & 0 deletions test/basic.d
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Expand Up @@ -68,6 +68,8 @@ enum platforms = [
Platform(Arch.mips, Mode.mips32r6 + Mode.mipsMicro + Mode.bigEndian, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"),
Platform(Arch.mips, Mode.mips32r6 + Mode.bigEndian, MIPS_32R6, "MIPS-32R6 (Big-endian)"),
Platform(Arch.arm64, Mode.arm, ARM64_CODE, "ARM-64"),
Platform(Arch.ppc, Mode.bigEndian, PPC_CODE, "PPC-64"),
Platform(Arch.ppc, Mode.bigEndian, PPC_CODE, "PPC-64, print register with number only", Syntax.noregname),
];

unittest{
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32 changes: 32 additions & 0 deletions test/basic.expected
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Expand Up @@ -139,3 +139,35 @@ Disasm:
0x100c: ldr w1, [sp, #8]
0x1010:

****************
Platform: PPC-64
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21
Disasm:
0x1000: lwz r1, 0(0)
0x1004: lwz r1, 0(r31)
0x1008: vpkpx v2, v3, v4
0x100c: stfs f2, 0x80(r4)
0x1010: crand 2, 3, 4
0x1014: cmpwi cr2, r3, 0x80
0x1018: addc r2, r3, r4
0x101c: mulhd. r2, r3, r4
0x1020: bdnzlrl+
0x1024: bgelrl- cr2
0x1028:

****************
Platform: PPC-64, print register with number only
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21
Disasm:
0x1000: lwz 1, 0(0)
0x1004: lwz 1, 0(31)
0x1008: vpkpx 2, 3, 4
0x100c: stfs 2, 0x80(4)
0x1010: crand 2, 3, 4
0x1014: cmpwi 2, 3, 0x80
0x1018: addc 2, 3, 4
0x101c: mulhd. 2, 3, 4
0x1020: bdnzlrl+
0x1024: bgelrl- cr2
0x1028:

6 changes: 5 additions & 1 deletion test/detail.d
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Expand Up @@ -65,6 +65,7 @@ enum platforms = [
Platform(Arch.mips, Mode.mips32r6 + Mode.mipsMicro + Mode.bigEndian, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"),
Platform(Arch.mips, Mode.mips32r6 + Mode.bigEndian, MIPS_32R6, "MIPS-32R6 (Big-endian)"),
Platform(Arch.arm64, Mode.arm, ARM64_CODE, "ARM-64"),
Platform(Arch.ppc, Mode.bigEndian, PPC_CODE, "PPC-64"),
];

void writeDetail(Arch arch)(ref OutBuffer buf, in InstructionImpl!arch instr, in CapstoneImpl!arch cs) {
Expand Down Expand Up @@ -116,7 +117,10 @@ unittest{
case Arch.mips:
buf.writeDetail(cast(InstructionImpl!(Arch.mips))instr, cast(CapstoneImpl!(Arch.mips))cs);
break;
case Arch.x86:
case Arch.ppc:
buf.writeDetail(cast(InstructionImpl!(Arch.ppc))instr, cast(CapstoneImpl!(Arch.ppc))cs);
break;
case Arch.x86:
buf.writeDetail(cast(InstructionImpl!(Arch.x86))instr, cast(CapstoneImpl!(Arch.x86))cs);
break;
default:
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26 changes: 26 additions & 0 deletions test/detail.expected
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Expand Up @@ -211,3 +211,29 @@ Disasm:
0x1040: ldr q16, [x24, w8, uxtw #4] // insn-ID: 162, insn-mnem: ldr
0x1044:

****************
Platform: PPC-64
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14
Disasm:
0x1000: lwz r1, 0(0) // insn-ID: 347, insn-mnem: lwz
0x1004: lwz r1, 0(r31) // insn-ID: 347, insn-mnem: lwz
0x1008: vpkpx v2, v3, v4 // insn-ID: 570, insn-mnem: vpkpx
This instruction belongs to groups: altivec
0x100c: stfs f2, 0x80(r4) // insn-ID: 443, insn-mnem: stfs
0x1010: crand 2, 3, 4 // insn-ID: 52, insn-mnem: crand
0x1014: cmpwi cr2, r3, 0x80 // insn-ID: 47, insn-mnem: cmpwi
0x1018: addc r2, r3, r4 // insn-ID: 2, insn-mnem: addc
Implicit registers modified: ca
0x101c: mulhd. r2, r3, r4 // insn-ID: 384, insn-mnem: mulhd
Implicit registers modified: cr0
0x1020: bdnzlrl+ // insn-ID: 28, insn-mnem: bdnzlrl
Implicit registers read: ctr lr rm
Implicit registers modified: ctr
0x1024: bgelrl- cr2 // insn-ID: 38, insn-mnem: blrl
Implicit registers read: ctr lr rm
Implicit registers modified: lr ctr
0x1028: bne 0x103c // insn-ID: 13, insn-mnem: b
Implicit registers read: ctr rm
Implicit registers modified: ctr
0x102c:

4 changes: 4 additions & 0 deletions test/iter.d
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Expand Up @@ -53,6 +53,7 @@ enum platforms = [
Platform(Arch.mips, Mode.mips32 + Mode.bigEndian, MIPS_CODE, "MIPS-32 (Big-endian)"),
Platform(Arch.mips, Mode.mips64 + Mode.littleEndian, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
Platform(Arch.arm64, Mode.arm, ARM64_CODE, "ARM-64"),
Platform(Arch.ppc, Mode.bigEndian, PPC_CODE, "PPC-64"),
];

void writeDetail(Arch arch)(ref OutBuffer buf, in InstructionImpl!arch instr, in CapstoneImpl!arch cs) {
Expand Down Expand Up @@ -101,6 +102,9 @@ unittest{
case Arch.mips:
buf.writeDetail(cast(InstructionImpl!(Arch.mips))instr, cast(CapstoneImpl!(Arch.mips))cs);
break;
case Arch.ppc:
buf.writeDetail(cast(InstructionImpl!(Arch.ppc))instr, cast(CapstoneImpl!(Arch.ppc))cs);
break;
case Arch.x86:
buf.writeDetail(cast(InstructionImpl!(Arch.x86))instr, cast(CapstoneImpl!(Arch.x86))cs);
break;
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25 changes: 25 additions & 0 deletions test/iter.expected
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Expand Up @@ -159,3 +159,28 @@ Disasm:
0x103c: add x0, x1, x2, lsl #2 // insn-ID: 6, insn-mnem: add
0x1040: ldr q16, [x24, w8, uxtw #4] // insn-ID: 162, insn-mnem: ldr

****************
Platform: PPC-64
Code: 0x80 0x20 0x00 0x00 0x80 0x3f 0x00 0x00 0x10 0x43 0x23 0x0e 0xd0 0x44 0x00 0x80 0x4c 0x43 0x22 0x02 0x2d 0x03 0x00 0x80 0x7c 0x43 0x20 0x14 0x7c 0x43 0x20 0x93 0x4f 0x20 0x00 0x21 0x4c 0xc8 0x00 0x21 0x40 0x82 0x00 0x14
Disasm:
0x1000: lwz r1, 0(0) // insn-ID: 347, insn-mnem: lwz
0x1004: lwz r1, 0(r31) // insn-ID: 347, insn-mnem: lwz
0x1008: vpkpx v2, v3, v4 // insn-ID: 570, insn-mnem: vpkpx
This instruction belongs to groups: altivec
0x100c: stfs f2, 0x80(r4) // insn-ID: 443, insn-mnem: stfs
0x1010: crand 2, 3, 4 // insn-ID: 52, insn-mnem: crand
0x1014: cmpwi cr2, r3, 0x80 // insn-ID: 47, insn-mnem: cmpwi
0x1018: addc r2, r3, r4 // insn-ID: 2, insn-mnem: addc
Implicit registers modified: ca
0x101c: mulhd. r2, r3, r4 // insn-ID: 384, insn-mnem: mulhd
Implicit registers modified: cr0
0x1020: bdnzlrl+ // insn-ID: 28, insn-mnem: bdnzlrl
Implicit registers read: ctr lr rm
Implicit registers modified: ctr
0x1024: bgelrl- cr2 // insn-ID: 38, insn-mnem: blrl
Implicit registers read: ctr lr rm
Implicit registers modified: lr ctr
0x1028: bne 0x103c // insn-ID: 13, insn-mnem: b
Implicit registers read: ctr rm
Implicit registers modified: ctr

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