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Merge pull request RIOT-OS#9698 from smlng/pr/cc2538/spi
cpu/cc2538: refine periph/spi implementation
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
|
|
@@ -14,6 +14,7 @@ | |
| * @brief CC2538 SSI interface | ||
| * | ||
| * @author Ian Martin <[email protected]> | ||
| * @author Sebastian Meiling <[email protected]> | ||
| */ | ||
|
|
||
| #ifndef CC2538_SSI_H | ||
|
|
@@ -29,92 +30,31 @@ extern "C" { | |
| * @brief SSI component registers | ||
| */ | ||
| typedef struct { | ||
| union { | ||
| cc2538_reg_t CR0; /**< SSI Control Register 0 */ | ||
| struct { | ||
| cc2538_reg_t DSS : 4; /**< SSI data size select */ | ||
| cc2538_reg_t FRF : 2; /**< SSI frame format select */ | ||
| cc2538_reg_t SPO : 1; /**< SSI serial clock polarity */ | ||
| cc2538_reg_t SPH : 1; /**< SSI serial clock phase */ | ||
| cc2538_reg_t SCR : 8; /**< SSI serial clock rate */ | ||
| cc2538_reg_t RESERVED : 16; /**< Reserved bits */ | ||
| } CR0bits; | ||
| }; | ||
|
|
||
| union { | ||
| cc2538_reg_t CR1; /**< SSI Control Register 1 */ | ||
| struct { | ||
| cc2538_reg_t LBM : 1; /**< SSI loop-back mode */ | ||
| cc2538_reg_t SSE : 1; /**< SSI synchronous serial port enable */ | ||
| cc2538_reg_t MS : 1; /**< SSI master and slave select */ | ||
| cc2538_reg_t SOD : 1; /**< SSI slave mode output disable */ | ||
| cc2538_reg_t RESERVED : 28; /**< Reserved bits */ | ||
| } CR1bits; | ||
| }; | ||
|
|
||
| cc2538_reg_t DR; /**< SSI Data register */ | ||
|
|
||
| union { | ||
| cc2538_reg_t SR; /**< SSI FIFO/busy Status Register */ | ||
| struct { | ||
| cc2538_reg_t TFE : 1; /**< SSI transmit FIFO empty */ | ||
| cc2538_reg_t TNF : 1; /**< SSI transmit FIFO not full */ | ||
| cc2538_reg_t RNE : 1; /**< SSI receive FIFO not empty */ | ||
| cc2538_reg_t RFF : 1; /**< SSI receive FIFO full */ | ||
| cc2538_reg_t BSY : 1; /**< SSI busy bit */ | ||
| cc2538_reg_t RESERVED : 27; /**< Reserved bits */ | ||
| } SRbits; | ||
| }; | ||
| cc2538_reg_t CPSR; /**< SSI Clock Register */ | ||
| cc2538_reg_t IM; /**< SSI Interrupt Mask register */ | ||
| cc2538_reg_t RIS; /**< SSI Raw Interrupt Status register */ | ||
| cc2538_reg_t MIS; /**< SSI Masked Interrupt Status register */ | ||
| cc2538_reg_t ICR; /**< SSI Interrupt Clear Register */ | ||
| cc2538_reg_t DMACTL; /**< SSI uDMA Control Register. */ | ||
| cc2538_reg_t CC; /**< SSI clock configuration */ | ||
| cc2538_reg_t CR0; /**< SSI Control Register 0 */ | ||
| cc2538_reg_t CR1; /**< SSI Control Register 1 */ | ||
| cc2538_reg_t DR; /**< SSI Data register */ | ||
| cc2538_reg_t SR; /**< SSI FIFO/busy Status Register */ | ||
| cc2538_reg_t CPSR; /**< SSI Clock Register */ | ||
| cc2538_reg_t IM; /**< SSI Interrupt Mask register */ | ||
| cc2538_reg_t RIS; /**< SSI Raw Interrupt Status register */ | ||
| cc2538_reg_t MIS; /**< SSI Masked Interrupt Status register */ | ||
| cc2538_reg_t ICR; /**< SSI Interrupt Clear Register */ | ||
| cc2538_reg_t DMACTL; /**< SSI uDMA Control Register. */ | ||
| cc2538_reg_t CC; /**< SSI clock configuration */ | ||
| } cc2538_ssi_t; | ||
|
|
||
| #define SSI0 ( (cc2538_ssi_t*)0x40008000 ) /**< SSI0 Instance */ | ||
| #define SSI1 ( (cc2538_ssi_t*)0x40009000 ) /**< SSI1 Instance */ | ||
|
|
||
| /** | ||
| * @brief Define CR0 register bitfields | ||
| * @{ | ||
| */ | ||
| #define SSI_CR0_DSS(x) ((x - 1) << 0) | ||
| #define SSI_CR0_SPO (1 << 6) | ||
| #define SSI_CR0_SPH (1 << 7) | ||
| /** @} */ | ||
|
|
||
| /** | ||
| * @brief Define CR1 register bitfields | ||
| * @{ | ||
| */ | ||
| #define SSI_CR1_LBM (1 << 0) | ||
| #define SSI_CR1_SSE (1 << 1) | ||
| #define SSI_CR1_MS (1 << 2) | ||
| #define SSI_CR1_SOD (1 << 3) | ||
| /** @} */ | ||
|
|
||
| /** | ||
| * @brief Define SR register bitfields | ||
| * @{ | ||
| * @brief Set CR0 data size (bits) | ||
| */ | ||
| #define SSI_SR_TFE (1 << 0) | ||
| #define SSI_SR_TNF (1 << 1) | ||
| #define SSI_SR_RNE (1 << 2) | ||
| #define SSI_SR_RFF (1 << 3) | ||
| #define SSI_SR_BSY (1 << 4) | ||
| /** @} */ | ||
| #define SSI_CR0_DSS(x) (x - 1) | ||
|
|
||
| /** | ||
| * @brief Define CC register bitfields | ||
| * @{ | ||
| */ | ||
| #define SSI_SS_PIOSC (1 << 0) | ||
| #define SSI_SS_DSEN (1 << 2) | ||
| #define SSI_SS_SYSDIV (0) | ||
| #define SSI_SS_IODIV (SSI_SS_PIOSC) | ||
| #define SSI_CC_CS_SYSDIV (0x0) | ||
| #define SSI_CC_CS_IODIV (0x1) | ||
| #define SSI_CC_CS_DSEN (0x4) | ||
| /** @} */ | ||
|
|
||
| #ifdef __cplusplus | ||
|
|
||
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