final edits

bytecodealliance · Jan 15, 2025 · cd24682 · cd24682
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Showing 11 changed files with 69 additions and 62 deletions.
diff --git a/tests/disas/winch/x64/atomic/load/i32_atomic_load.wat b/tests/disas/winch/x64/atomic/load/i32_atomic_load.wat
@@ -13,23 +13,23 @@
 ;;       movq    0x10(%r11), %r11
 ;;       addq    $0x20, %r11
 ;;       cmpq    %rsp, %r11
-;;       ja      0x58
+;;       ja      0x57
 ;;   1c: movq    %rdi, %r14
 ;;       subq    $0x20, %rsp
 ;;       movq    %rdi, 0x18(%rsp)
 ;;       movq    %rsi, 0x10(%rsp)
 ;;       movl    %edx, 0xc(%rsp)
 ;;       movl    0xc(%rsp), %eax
-;;       movl    %eax, %r11d
-;;       andl    $3, %r11d
-;;       cmpl    $0, %r11d
-;;       jne     0x5a
-;;   46: movq    0x58(%r14), %r11
+;;       andl    $3, %eax
+;;       cmpl    $0, %eax
+;;       jne     0x59
+;;   41: movl    0xc(%rsp), %eax
+;;       movq    0x58(%r14), %r11
 ;;       movq    (%r11), %rcx
 ;;       addq    %rax, %rcx
 ;;       movl    (%rcx), %eax
 ;;       addq    $0x20, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   58: ud2
-;;   5a: ud2
+;;   57: ud2
+;;   59: ud2
diff --git a/tests/disas/winch/x64/atomic/load/i32_atomic_load16_u.wat b/tests/disas/winch/x64/atomic/load/i32_atomic_load16_u.wat
@@ -13,23 +13,23 @@
 ;;       movq    0x10(%r11), %r11
 ;;       addq    $0x20, %r11
 ;;       cmpq    %rsp, %r11
-;;       ja      0x5c
+;;       ja      0x5b
 ;;   1c: movq    %rdi, %r14
 ;;       subq    $0x20, %rsp
 ;;       movq    %rdi, 0x18(%rsp)
 ;;       movq    %rsi, 0x10(%rsp)
 ;;       movl    %edx, 0xc(%rsp)
 ;;       movl    0xc(%rsp), %eax
-;;       movl    %eax, %r11d
-;;       andw    $1, %r11w
-;;       cmpw    $0, %r11w
-;;       jne     0x5e
-;;   48: movq    0x58(%r14), %r11
+;;       andw    $1, %ax
+;;       cmpw    $0, %ax
+;;       jne     0x5d
+;;   43: movl    0xc(%rsp), %eax
+;;       movq    0x58(%r14), %r11
 ;;       movq    (%r11), %rcx
 ;;       addq    %rax, %rcx
 ;;       movzwq  (%rcx), %rax
 ;;       addq    $0x20, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   5c: ud2
-;;   5e: ud2
+;;   5b: ud2
+;;   5d: ud2
diff --git a/tests/disas/winch/x64/atomic/load/i64_atomic_load.wat b/tests/disas/winch/x64/atomic/load/i64_atomic_load.wat
@@ -14,21 +14,21 @@
 ;;       movq    0x10(%r11), %r11
 ;;       addq    $0x10, %r11
 ;;       cmpq    %rsp, %r11
-;;       ja      0x52
+;;       ja      0x54
 ;;   1c: movq    %rdi, %r14
 ;;       subq    $0x10, %rsp
 ;;       movq    %rdi, 8(%rsp)
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0, %eax
-;;       movq    %rax, %r11
-;;       andq    $7, %r11
-;;       cmpq    $0, %r11
-;;       jne     0x54
-;;   42: movq    0x60(%r14), %rcx
+;;       andq    $7, %rax
+;;       cmpq    $0, %rax
+;;       jne     0x56
+;;   3f: movl    $0, %eax
+;;       movq    0x60(%r14), %rcx
 ;;       addq    %rax, %rcx
 ;;       movq    (%rcx), %rax
 ;;       addq    $0x10, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   52: ud2
 ;;   54: ud2
+;;   56: ud2
diff --git a/tests/disas/winch/x64/atomic/load/i64_atomic_load16_u.wat b/tests/disas/winch/x64/atomic/load/i64_atomic_load16_u.wat
@@ -20,11 +20,11 @@
 ;;       movq    %rdi, 8(%rsp)
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0, %eax
-;;       movl    %eax, %r11d
-;;       andw    $1, %r11w
-;;       cmpw    $0, %r11w
+;;       andw    $1, %ax
+;;       cmpw    $0, %ax
 ;;       jne     0x57
-;;   44: movq    0x60(%r14), %rcx
+;;   3f: movl    $0, %eax
+;;       movq    0x60(%r14), %rcx
 ;;       addq    %rax, %rcx
 ;;       movzwq  (%rcx), %rax
 ;;       addq    $0x10, %rsp

diff --git a/tests/disas/winch/x64/atomic/load/i64_atomic_load32_u.wat b/tests/disas/winch/x64/atomic/load/i64_atomic_load32_u.wat
@@ -20,11 +20,11 @@
 ;;       movq    %rdi, 8(%rsp)
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0, %eax
-;;       movl    %eax, %r11d
-;;       andl    $3, %r11d
-;;       cmpl    $0, %r11d
+;;       andl    $3, %eax
+;;       cmpl    $0, %eax
 ;;       jne     0x53
-;;   42: movq    0x60(%r14), %rcx
+;;   3d: movl    $0, %eax
+;;       movq    0x60(%r14), %rcx
 ;;       addq    %rax, %rcx
 ;;       movl    (%rcx), %eax
 ;;       addq    $0x10, %rsp

diff --git a/tests/disas/winch/x64/atomic/store/i32_atomic_store.wat b/tests/disas/winch/x64/atomic/store/i32_atomic_store.wat
@@ -18,11 +18,11 @@
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0x2a, %eax
 ;;       movl    $0, %ecx
-;;       movl    %ecx, %r11d
-;;       andl    $3, %r11d
-;;       cmpl    $0, %r11d
+;;       andl    $3, %ecx
+;;       cmpl    $0, %ecx
 ;;       jne     0x5e
-;;   47: movq    0x58(%r14), %r11
+;;   42: movl    $0, %ecx
+;;       movq    0x58(%r14), %r11
 ;;       movq    (%r11), %rdx
 ;;       addq    %rcx, %rdx
 ;;       movl    %eax, (%rdx)

diff --git a/tests/disas/winch/x64/atomic/store/i32_atomic_store16.wat b/tests/disas/winch/x64/atomic/store/i32_atomic_store16.wat
@@ -18,11 +18,11 @@
 ;;       movq    %rsi, (%rsp)
 ;;       movl    $0x2a, %eax
 ;;       movl    $0, %ecx
-;;       movl    %ecx, %r11d
-;;       andw    $1, %r11w
-;;       cmpw    $0, %r11w
+;;       andw    $1, %cx
+;;       cmpw    $0, %cx
 ;;       jne     0x61
-;;   49: movq    0x58(%r14), %r11
+;;   44: movl    $0, %ecx
+;;       movq    0x58(%r14), %r11
 ;;       movq    (%r11), %rdx
 ;;       addq    %rcx, %rdx
 ;;       movw    %ax, (%rdx)

diff --git a/tests/disas/winch/x64/atomic/store/i64_atomic_store.wat b/tests/disas/winch/x64/atomic/store/i64_atomic_store.wat
@@ -11,24 +11,24 @@
 ;;       movq    0x10(%r11), %r11
 ;;       addq    $0x10, %r11
 ;;       cmpq    %rsp, %r11
-;;       ja      0x5f
+;;       ja      0x61
 ;;   1c: movq    %rdi, %r14
 ;;       subq    $0x10, %rsp
 ;;       movq    %rdi, 8(%rsp)
 ;;       movq    %rsi, (%rsp)
 ;;       movq    $0x2a, %rax
 ;;       movl    $0, %ecx
-;;       movq    %rcx, %r11
-;;       andq    $7, %r11
-;;       cmpq    $0, %r11
-;;       jne     0x61
-;;   49: movq    0x58(%r14), %r11
+;;       andq    $7, %rcx
+;;       cmpq    $0, %rcx
+;;       jne     0x63
+;;   46: movl    $0, %ecx
+;;       movq    0x58(%r14), %r11
 ;;       movq    (%r11), %rdx
 ;;       addq    %rcx, %rdx
 ;;       movq    %rax, (%rdx)
 ;;       mfence
 ;;       addq    $0x10, %rsp
 ;;       popq    %rbp
 ;;       retq
-;;   5f: ud2
 ;;   61: ud2
+;;   63: ud2
diff --git a/tests/disas/winch/x64/atomic/store/i64_atomic_store16.wat b/tests/disas/winch/x64/atomic/store/i64_atomic_store16.wat
@@ -18,11 +18,11 @@
 ;;       movq    %rsi, (%rsp)
 ;;       movq    $0x2a, %rax
 ;;       movl    $0, %ecx
-;;       movl    %ecx, %r11d
-;;       andw    $1, %r11w
-;;       cmpw    $0, %r11w
+;;       andw    $1, %cx
+;;       cmpw    $0, %cx
 ;;       jne     0x63
-;;   4b: movq    0x58(%r14), %r11
+;;   46: movl    $0, %ecx
+;;       movq    0x58(%r14), %r11
 ;;       movq    (%r11), %rdx
 ;;       addq    %rcx, %rdx
 ;;       movw    %ax, (%rdx)

diff --git a/tests/disas/winch/x64/atomic/store/i64_atomic_store32.wat b/tests/disas/winch/x64/atomic/store/i64_atomic_store32.wat
@@ -18,11 +18,11 @@
 ;;       movq    %rsi, (%rsp)
 ;;       movq    $0x2a, %rax
 ;;       movl    $0, %ecx
-;;       movl    %ecx, %r11d
-;;       andl    $3, %r11d
-;;       cmpl    $0, %r11d
+;;       andl    $3, %ecx
+;;       cmpl    $0, %ecx
 ;;       jne     0x60
-;;   49: movq    0x58(%r14), %r11
+;;   44: movl    $0, %ecx
+;;       movq    0x58(%r14), %r11
 ;;       movq    (%r11), %rdx
 ;;       addq    %rcx, %rdx
 ;;       movl    %eax, (%rdx)

diff --git a/winch/codegen/src/codegen/mod.rs b/winch/codegen/src/codegen/mod.rs
@@ -844,11 +844,13 @@ where
     fn emit_check_align(&mut self, memarg: &MemArg, size: OperandSize) -> Result<()> {
         if size.bytes() > 1 {
             // Peek addr from top of the stack by popping and pushing.
-            let addr = self.context.pop_to_reg(self.masm, None)?;
-            self.context.stack.push(addr.into());
-
-            let tmp = scratch!(M);
-            self.masm.mov(writable!(tmp), RegImm::Reg(addr.reg), size)?;
+            let addr = *self
+                .context
+                .stack
+                .peek()
+                .ok_or_else(|| CodeGenError::missing_values_in_stack())?;
+            let tmp = self.context.any_gpr(self.masm)?;
+            self.context.move_val_to_reg(&addr, tmp, self.masm)?;
 
             if memarg.offset != 0 {
                 self.masm.add(
@@ -868,6 +870,7 @@ where
 
             self.masm.cmp(tmp, RegImm::Imm(Imm::i64(0)), size)?;
             self.masm.trapif(IntCmpKind::Ne, TRAP_HEAP_MISALIGNED)?;
+            self.context.free_reg(tmp);
         }
 
         Ok(())
@@ -891,12 +894,16 @@ where
         op_kind: MemOpKind,
     ) -> Result<()> {
         let maybe_addr = match op_kind {
-            MemOpKind::Atomic => self.emit_compute_heap_address_align_checked(&arg, kind.derive_operand_size())?,
-            MemOpKind::Normal => self.emit_compute_heap_address(&arg, kind.derive_operand_size())?,
+            MemOpKind::Atomic => {
+                self.emit_compute_heap_address_align_checked(&arg, kind.derive_operand_size())?
+            }
+            MemOpKind::Normal => {
+                self.emit_compute_heap_address(&arg, kind.derive_operand_size())?
+            }
         };
 
         if let Some(addr) = maybe_addr {
-            let dst = match target_ty {
+            let dst = match target_type {
                 WasmValType::I32 | WasmValType::I64 => self.context.any_gpr(self.masm)?,
                 WasmValType::F32 | WasmValType::F64 => self.context.any_fpr(self.masm)?,
                 WasmValType::V128 => self.context.reg_for_type(target_type, self.masm)?,