Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Make Pulley pass simd_f32x4_arith.wast #9897

Merged
merged 3 commits into from
Jan 6, 2025
Merged

Make Pulley pass simd_f32x4_arith.wast #9897

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
55523db
Add f32x4 arithmetic instructions to Pulley:
tyoeer Dec 23, 2024
d910101
Mark `simd_f32x4_arith.wast` as passing for Pulley:
tyoeer Dec 23, 2024
e6ca3d1
Rename 2 f32x4 arithmatic instructions to contain "f32x4":
tyoeer Jan 2, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 3 additions & 0 deletions cranelift/codegen/src/isa/pulley_shared/lower.isle
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1157,12 +1157,14 @@

(rule (lower (has_type $F32 (fsub a b))) (pulley_fsub32 a b))
(rule (lower (has_type $F64 (fsub a b))) (pulley_fsub64 a b))
(rule (lower (has_type $F32X4 (fsub a b))) (pulley_vsubf32x4 a b))
(rule (lower (has_type $F64X2 (fsub a b))) (pulley_vsubf64x2 a b))

;;;; Rules for `fmul` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

(rule (lower (has_type $F32 (fmul a b))) (pulley_fmul32 a b))
(rule (lower (has_type $F64 (fmul a b))) (pulley_fmul64 a b))
(rule (lower (has_type $F32X4 (fmul a b))) (pulley_vmulf32x4 a b))
(rule (lower (has_type $F64X2 (fmul a b))) (pulley_vmulf64x2 a b))

;;;; Rules for `fdiv` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Expand Down Expand Up @@ -1233,6 +1235,7 @@

(rule (lower (has_type $F32 (fneg a))) (pulley_fneg32 a))
(rule (lower (has_type $F64 (fneg a))) (pulley_fneg64 a))
(rule (lower (has_type $F32X4 (fneg a))) (pulley_vnegf32x4 a))
(rule (lower (has_type $F64X2 (fneg a))) (pulley_vnegf64x2 a))

;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Expand Down
1 change: 0 additions & 1 deletion crates/wast-util/src/lib.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -408,7 +408,6 @@ impl WastTest {
"spec_testsuite/proposals/relaxed-simd/relaxed_madd_nmadd.wast",
"spec_testsuite/proposals/memory64/relaxed_madd_nmadd.wast",
"spec_testsuite/proposals/memory64/i32x4_relaxed_trunc.wast",
"spec_testsuite/simd_f32x4_arith.wast",
"spec_testsuite/simd_f32x4_cmp.wast",
"spec_testsuite/simd_f32x4_pmin_pmax.wast",
"spec_testsuite/simd_f64x2_cmp.wast",
Expand Down
29 changes: 29 additions & 0 deletions pulley/src/interp.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2980,13 +2980,33 @@ impl ExtendedOpVisitor for Interpreter<'_> {
ControlFlow::Continue(())
}

fn vsubf32x4(&mut self, operands: BinaryOperands<VReg>) -> ControlFlow<Done> {
let mut a = self.state[operands.src1].get_f32x4();
let b = self.state[operands.src2].get_f32x4();
for (a, b) in a.iter_mut().zip(b) {
*a = *a - b;
}
self.state[operands.dst].set_f32x4(a);
ControlFlow::Continue(())
}

fn fmul32(&mut self, operands: BinaryOperands<FReg>) -> ControlFlow<Done> {
let a = self.state[operands.src1].get_f32();
let b = self.state[operands.src2].get_f32();
self.state[operands.dst].set_f32(a * b);
ControlFlow::Continue(())
}

fn vmulf32x4(&mut self, operands: BinaryOperands<VReg>) -> ControlFlow<Done> {
let mut a = self.state[operands.src1].get_f32x4();
let b = self.state[operands.src2].get_f32x4();
for (a, b) in a.iter_mut().zip(b) {
*a = *a * b;
}
self.state[operands.dst].set_f32x4(a);
ControlFlow::Continue(())
}

fn fdiv32(&mut self, operands: BinaryOperands<FReg>) -> ControlFlow<Done> {
let a = self.state[operands.src1].get_f32();
let b = self.state[operands.src2].get_f32();
Expand Down Expand Up @@ -3162,6 +3182,15 @@ impl ExtendedOpVisitor for Interpreter<'_> {
ControlFlow::Continue(())
}

fn vnegf32x4(&mut self, dst: VReg, src: VReg) -> ControlFlow<Done> {
let mut a = self.state[src].get_f32x4();
for elem in a.iter_mut() {
*elem = -*elem;
}
self.state[dst].set_f32x4(a);
ControlFlow::Continue(())
}

fn fabs32(&mut self, dst: FReg, src: FReg) -> ControlFlow<Done> {
let a = self.state[src].get_f32();
self.state[dst].set_f32(a.wasm_abs());
Expand Down
6 changes: 6 additions & 0 deletions pulley/src/lib.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -811,8 +811,12 @@ macro_rules! for_each_extended_op {
fadd32 = Fadd32 { operands: BinaryOperands<FReg> };
/// `low32(dst) = low32(src1) - low32(src2)`
fsub32 = Fsub32 { operands: BinaryOperands<FReg> };
/// `low128(dst) = low128(src1) - low128(src2)`
vsubf32x4 = Vsubf32x4 { operands: BinaryOperands<VReg> };
/// `low32(dst) = low32(src1) * low32(src2)`
fmul32 = Fmul32 { operands: BinaryOperands<FReg> };
/// `low128(dst) = low128(src1) * low128(src2)`
vmulf32x4 = Vmulf32x4 { operands: BinaryOperands<VReg> };
/// `low32(dst) = low32(src1) / low32(src2)`
fdiv32 = Fdiv32 { operands: BinaryOperands<FReg> };
/// `low128(dst) = low128(src1) / low128(src2)`
Expand Down Expand Up @@ -849,6 +853,8 @@ macro_rules! for_each_extended_op {
vsqrt64x2 = Vsqrt64x2 { dst: VReg, src: VReg };
/// `low32(dst) = -low32(src)`
fneg32 = Fneg32 { dst: FReg, src: FReg };
/// `low128(dst) = -low128(src)`
vnegf32x4 = Vnegf32x4 { dst: VReg, src: VReg };
/// `low32(dst) = |low32(src)|`
fabs32 = Fabs32 { dst: FReg, src: FReg };

Expand Down
Loading