Add supports to DVP (#14)

* add dvp supports --------- Co-authored-by: Andelf <[email protected]>
ch32-rs · Nov 9, 2024 · ea7624e · ea7624e
1 parent 3ce4cce
commit ea7624e
Show file tree

Hide file tree

Showing 4 changed files with 413 additions and 0 deletions.
diff --git a/data/chips/CH32V307VCT6.yaml b/data/chips/CH32V307VCT6.yaml
@@ -76,6 +76,7 @@ cores:
       - "../peripherals/FV2x_V3x_SDIO.yaml"
       - "../peripherals/FV2x_V3x_CAN1.yaml"
       - "../peripherals/FV2x_V3x_CAN2.yaml"
+      - "../peripherals/V3x_DVP.yaml"
 
     include_interrupts: "../interrupts/CH32V3.yaml"
     include_dma_channels:

diff --git a/data/interrupts/CH32V3.yaml b/data/interrupts/CH32V3.yaml
@@ -127,6 +127,8 @@ OTG_FS: 83
 USBHS_WKUP: 84
 # 85 - USBHS
 USBHS: 85
+# 86 - DVP global interrupt
+DVP: 86
 # 87 - USART6 global interrupt
 USART6: 87
 # 88 - USART7 global interrupt

diff --git a/data/peripherals/V3x_DVP.yaml b/data/peripherals/V3x_DVP.yaml
@@ -0,0 +1,49 @@
+- name: DVP
+  address: 0x50050000
+  registers:
+    kind: dvp
+    version: v3
+    block: DVP
+  rcc:
+    bus_clock: HCLK
+    kernel_clock: HCLK
+    enable:
+      register: AHBPCENR
+      field: DVP_EN
+    reset:
+      register: AHBRSTR
+      field: DVPRST
+  interrupts:
+    - signal: GLOBAL
+      interrupt: DVP
+  pins:
+    - pin: PA4
+      signal: HSYNC
+    - pin: PA5
+      signal: VSYNC
+    - pin: PA6
+      signal: PCLK
+    - pin: PA9
+      signal: D0
+    - pin: PA10
+      signal: D1
+    - pin: PC8
+      signal: D2
+    - pin: PC9
+      signal: D3
+    - pin: PC11
+      signal: D4
+    - pin: PB6
+      signal: D5
+    - pin: PB8
+      signal: D6
+    - pin: PB9
+      signal: D7
+    - pin: PC10
+      signal: D8
+    - pin: PC12
+      signal: D9
+    - pin: PD6
+      signal: D10
+    - pin: PD2
+      signal: D11