[rtl] add zvma. #957
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[rtl] add zvma. #957
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sequencer
requested changes
Jan 24, 2025
| } | ||
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| class ZVMAInstRequest(parameter: ZVMAParameter) extends Bundle { | ||
| val instruction: UInt = UInt(32.W) |
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add index, the zvma will be dec at vector decode stage.
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Require should contain all metadata that required by zmva block
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| // TEW = SEW * TWIDEN | ||
| val tew = UInt(3.W) | ||
| // tk can hold values from 0-4, inclusive. | ||
| val tk = UInt(3.W) | ||
| // tm can hold values from 0-TE, inclusive. | ||
| val tm = UInt(parameter.tmWidth.W) | ||
| val tn = UInt(parameter.tnWidth.W) |
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| val dataFromLSU: ValidIO[ZVMADataChannel] = Flipped(Valid(new ZVMADataChannel(parameter))) | ||
| val dataToLSU: DecoupledIO[ZVMADataChannel] = Decoupled(new ZVMADataChannel(parameter)) |
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Read/Write Channel not only for LSU, but operand
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