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Add RISC-V MachRegister Unit Test #14

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Add RISC-V MachRegister Unit Test #14

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5 changes: 5 additions & 0 deletions MachRegister/base_registers/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,11 @@ target_include_directories(basereg_ppc32 PRIVATE ${UNIT_TESTS_INCLUDES})
target_link_libraries(basereg_ppc32 PRIVATE Dyninst::common)
add_test(NAME machregister_basereg_ppc32 COMMAND basereg_ppc32)

add_executable(basereg_riscv64 riscv64.cpp)
target_compile_options(basereg_riscv64 PRIVATE ${UNIT_TESTS_WARNING_FLAGS})
target_include_directories(basereg_riscv64 PRIVATE ${UNIT_TESTS_INCLUDES})
target_link_libraries(basereg_riscv64 PRIVATE Dyninst::common)
add_test(NAME machregister_basereg_riscv64 COMMAND basereg_riscv64)

# These are disabled until we can decide on how to represent base registers for AMDGPU
add_executable(basereg_amdgpu_gfx908 amdgpu_gfx908.cpp)
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27 changes: 27 additions & 0 deletions MachRegister/base_registers/riscv64.cpp
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Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@
#include "basereg_check.h"
#include "registers/riscv64_regs.h"

int main() {

// GPR 64 -> 64
BASEREG_CHECK(riscv64::x0, riscv64::x0);
BASEREG_CHECK(riscv64::x8, riscv64::x0);
BASEREG_CHECK(riscv64::x31, riscv64::x0);

// FPR 32 -> *
BASEREG_CHECK(riscv64::f0_32, riscv64::f0);
BASEREG_CHECK(riscv64::f8_32, riscv64::f0);
BASEREG_CHECK(riscv64::f31_32, riscv64::f0);

// FPR 64 -> *
BASEREG_CHECK(riscv64::f0_64, riscv64::f0);
BASEREG_CHECK(riscv64::f8_64, riscv64::f0);
BASEREG_CHECK(riscv64::f31_64, riscv64::f0);

// FPR * -> *
BASEREG_CHECK(riscv64::f0, riscv64::f0);
BASEREG_CHECK(riscv64::f8, riscv64::f0);
BASEREG_CHECK(riscv64::f31, riscv64::f0);

return EXIT_SUCCESS;
}
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