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Status_Matrix
Ali edited this page May 12, 2018
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The follow six tables describe the current state of component combinations in gem5.
| Definitely does not work |
| Might work |
| Should work |
| Definitely works |
| Unknown |
Below Classic and Ruby refers to the two memory systems that we have in gem5. MI, MESI and MOESI (multiple flavors) are the coherence protocols that are supported in Ruby memory system. Then we have the CPU models: AtomicSimple, TimingSimple, InOrder and O3.
Numbers in the squares below refer to the following notes:
- Ruby does not support atomic-mode accesses
- The MI_example protocol cannot support LL/SC semantics
- Classic caches do not support x86 locked (atomic RMW) accesses. The AtomicSimple CPU model enforces atomic RMW accesses itself, so this only affects correctness for timing-mode CPU models.
THIS PAGE WAS LAST UPDATED IN 2015. IT IS LIKELY OUT OF DATE. USE THIS AS A GUIDELINE.
| Processor | Memory System |
|---|---|
| Model | System |
| MI_example | MOESI_hammer |
| AtomicSimple | SE |
| multi | |
| FS | uni |
| multi | |
| TimingSimple | SE |
| multi | |
| FS | uni |
| multi | |
| InOrder | SE |
| multi | |
| FS | uni |
| multi | |
| O3 | SE |
| multi | |
| FS | uni |
| multi | |
| Processor | Memory System |
|---|---|
| Model | System |
| MI_example | MOESI_hammer |
| AtomicSimple | SE |
| multi | |
| FS | uni |
| multi | |
| TimingSimple | SE |
| multi | |
| FS | uni |
| multi | |
| InOrder | SE |
| multi | |
| FS | uni |
| multi | |
| O3 | SE |
| multi | |
| FS | uni |
| multi | |
| Processor | Memory System |
|---|---|
| Model | System |
| MI_example | MOESI_hammer |
| AtomicSimple | SE |
| multi | |
| FS | uni |
| multi | |
| TimingSimple | SE |
| multi | Note 3 |
| FS | uni |
| multi | Note 3 |
| InOrder | SE |
| multi | |
| FS | uni |
| multi | |
| O3 | SE |
| multi | Note 3 |
| FS | uni |
| multi | Note 3 |
| Processor | Memory System |
|---|---|
| Model | System |
| MI_example | MOESI_hammer |
| AtomicSimple | SE |
| multi | |
| FS | uni |
| multi | |
| TimingSimple | SE |
| multi | |
| FS | uni |
| multi | |
| InOrder | SE |
| multi | |
| FS | uni |
| multi | |
| O3 | SE |
| multi | |
| FS | uni |
| multi | |
| Processor | Memory System |
|---|---|
| Model | System |
| MI_example | MOESI_hammer |
| AtomicSimple | SE |
| multi | |
| FS | uni |
| multi | |
| TimingSimple | SE |
| multi | |
| FS | uni |
| multi | |
| InOrder | SE |
| multi | |
| FS | uni |
| multi | |
| O3 | SE |
| multi | |
| FS | uni |
| multi | |
| Processor | Memory System |
|---|---|
| Model | System |
| MI_example | MOESI_hammer |
| AtomicSimple | SE |
| multi | |
| FS | uni |
| multi | |
| TimingSimple | SE |
| multi | |
| FS | uni |
| multi | |
| InOrder | SE |
| multi | |
| FS | uni |
| multi | |
| O3 | SE |
| multi | |
| FS | uni |
| multi | |