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fix decoding of control registers
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felipesanches committed Dec 31, 2023
1 parent 327ec67 commit 490608c
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Showing 2 changed files with 124 additions and 60 deletions.
178 changes: 118 additions & 60 deletions src/devices/cpu/tlcs900/dasm900.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1519,6 +1519,115 @@ u32 tlcs900_disassembler::opcode_alignment() const
return 1;
}

void tlcs900_disassembler::decode_control_register_8(std::ostream &stream, uint32_t imm){
switch( imm )
{
case 0x22: util::stream_format(stream, " DMAM0"); break;
case 0x26: util::stream_format(stream, " DMAM1"); break;
case 0x2a: util::stream_format(stream, " DMAM2"); break;
case 0x2e: util::stream_format(stream, " DMAM3"); break;
default:
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
break;
}
}


void tmp94c241_disassembler::decode_control_register_8(std::ostream &stream, uint32_t imm){
switch( imm )
{
case 0x42: util::stream_format(stream, " DMAM0"); break;
case 0x46: util::stream_format(stream, " DMAM1"); break;
case 0x4a: util::stream_format(stream, " DMAM2"); break;
case 0x4e: util::stream_format(stream, " DMAM3"); break;
case 0x52: util::stream_format(stream, " DMAM4"); break;
case 0x56: util::stream_format(stream, " DMAM5"); break;
case 0x5a: util::stream_format(stream, " DMAM6"); break;
case 0x5e: util::stream_format(stream, " DMAM7"); break;
default:
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
break;
}
}


void tlcs900_disassembler::decode_control_register_16(std::ostream &stream, uint32_t imm){
switch( imm )
{
case 0x20: util::stream_format(stream, " DMAC0"); break;
case 0x24: util::stream_format(stream, " DMAC1"); break;
case 0x28: util::stream_format(stream, " DMAC2"); break;
case 0x2c: util::stream_format(stream, " DMAC3"); break;
case 0x7c: util::stream_format(stream, " NSP"); break;
default:
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
break;
}
}


void tmp94c241_disassembler::decode_control_register_16(std::ostream &stream, uint32_t imm){
switch( imm )
{
case 0x40: util::stream_format(stream, " DMAC0"); break;
case 0x44: util::stream_format(stream, " DMAC1"); break;
case 0x48: util::stream_format(stream, " DMAC2"); break;
case 0x4c: util::stream_format(stream, " DMAC3"); break;
case 0x50: util::stream_format(stream, " DMAC4"); break;
case 0x54: util::stream_format(stream, " DMAC5"); break;
case 0x58: util::stream_format(stream, " DMAC6"); break;
case 0x5c: util::stream_format(stream, " DMAC7"); break;
default:
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
break;
}
}


void tlcs900_disassembler::decode_control_register_32(std::ostream &stream, uint32_t imm){
switch( imm )
{
case 0x00: util::stream_format(stream, " DMAS0"); break;
case 0x04: util::stream_format(stream, " DMAS1"); break;
case 0x08: util::stream_format(stream, " DMAS2"); break;
case 0x0c: util::stream_format(stream, " DMAS3"); break;
case 0x10: util::stream_format(stream, " DMAD0"); break;
case 0x14: util::stream_format(stream, " DMAD1"); break;
case 0x18: util::stream_format(stream, " DMAD2"); break;
case 0x1c: util::stream_format(stream, " DMAD3"); break;
default:
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
break;
}
}


void tmp94c241_disassembler::decode_control_register_32(std::ostream &stream, uint32_t imm){
switch( imm )
{
case 0x00: util::stream_format(stream, " DMAS0"); break;
case 0x04: util::stream_format(stream, " DMAS1"); break;
case 0x08: util::stream_format(stream, " DMAS2"); break;
case 0x0c: util::stream_format(stream, " DMAS3"); break;
case 0x10: util::stream_format(stream, " DMAS4"); break;
case 0x14: util::stream_format(stream, " DMAS5"); break;
case 0x18: util::stream_format(stream, " DMAS6"); break;
case 0x1c: util::stream_format(stream, " DMAS7"); break;
case 0x20: util::stream_format(stream, " DMAD0"); break;
case 0x24: util::stream_format(stream, " DMAD1"); break;
case 0x28: util::stream_format(stream, " DMAD2"); break;
case 0x2c: util::stream_format(stream, " DMAD3"); break;
case 0x30: util::stream_format(stream, " DMAD4"); break;
case 0x34: util::stream_format(stream, " DMAD5"); break;
case 0x38: util::stream_format(stream, " DMAD6"); break;
case 0x3c: util::stream_format(stream, " DMAD7"); break;
default:
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
break;
}
}


offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
{
const tlcs900inst *dasm;
Expand Down Expand Up @@ -2048,44 +2157,17 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const

case O_CR8:
imm = opcodes.r8( pos++ );
switch(imm & 0xe3)
{
case 0x42:
util::stream_format(stream, " DMAM%d", (imm >> 2) & 7);
break;
default:
util::stream_format(stream, " <Unknown 8-bit ControlReg 0x%02X>", imm);
break;
}
decode_control_register_8(stream, imm);
break;

case O_CR16:
imm = opcodes.r8( pos++ );
switch(imm & 0xe3)
{
case 0x40:
util::stream_format(stream, " DMAC%d", (imm >> 2) & 7);
break;
default:
util::stream_format(stream, " <Unknown 16-bit ControlReg 0x%02X>", imm);
break;
}
decode_control_register_16(stream, imm);
break;

case O_CR32:
imm = opcodes.r8( pos++ );
switch( imm & 0xe3 )
{
case 0x00:
util::stream_format(stream, " DMAS%d", (imm >> 2) & 7);
break;
case 0x20:
util::stream_format(stream, " DMAD%d", (imm >> 2) & 7);
break;
default:
util::stream_format(stream, " <Unknown 32-bit ControlReg 0x%02X>", imm);
break;
}
decode_control_register_32(stream, imm);
break;

case O_D8:
Expand Down Expand Up @@ -2216,44 +2298,20 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const

case O_CR8:
imm = opcodes.r8( pos++ );
switch( imm & 0xe3 )
{
case 0x42:
util::stream_format(stream, ",DMAM%d", (imm >> 2) & 7);
break;
default:
util::stream_format(stream, ",<Unknown 8-bit ControlReg 0x%02X>", imm);
break;
}
util::stream_format(stream, ",");
decode_control_register_8(stream, imm);
break;

case O_CR16:
imm = opcodes.r8( pos++ );
switch( imm & 0xe3 )
{
case 0x40:
util::stream_format(stream, ",DMAC%d", (imm >> 2) & 7);
break;
default:
util::stream_format(stream, ",<Unknown 16-bit ControlReg 0x%02X>", imm);
break;
}
util::stream_format(stream, ",");
decode_control_register_16(stream, imm);
break;

case O_CR32:
imm = opcodes.r8( pos++ );
switch( imm & 0xe3 )
{
case 0x00:
util::stream_format(stream, ",DMAS%d", (imm >> 2) & 7);
break;
case 0x20:
util::stream_format(stream, ",DMAD%d", (imm >> 2) & 7);
break;
default:
util::stream_format(stream, ",<Unknown 32-bit ControlReg 0x%02X>", imm);
break;
}
util::stream_format(stream, ",");
decode_control_register_32(stream, imm);
break;

case O_D8:
Expand Down
6 changes: 6 additions & 0 deletions src/devices/cpu/tlcs900/dasm900.h
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,9 @@ class tlcs900_disassembler : public util::disasm_interface
{
protected:
tlcs900_disassembler(uint16_t num_sfr, const char *const sfr_names[]);
void decode_control_register_8(std::ostream &stream, uint32_t imm);
void decode_control_register_16(std::ostream &stream, uint32_t imm);
void decode_control_register_32(std::ostream &stream, uint32_t imm);

public:
virtual ~tlcs900_disassembler() = default;
Expand Down Expand Up @@ -117,6 +120,9 @@ class tmp94c241_disassembler : public tlcs900_disassembler
{
public:
tmp94c241_disassembler();
void decode_control_register_8(std::ostream &stream, uint32_t imm);
void decode_control_register_16(std::ostream &stream, uint32_t imm);
void decode_control_register_32(std::ostream &stream, uint32_t imm);

private:
static const char *const s_sfr_names[];
Expand Down

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