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commit ddbe48383984d56acd9e1ab6a090c54ca6b735a6 Author: Jean-Marc Valin <[email protected]> Date: Wed Apr 10 16:38:50 2024 -0400 Update DRED REDME.md commit b7e1c4f0aa15100a4cf1a36d4d46aae790d271f4 Author: Jean-Marc Valin <[email protected]> Date: Wed Apr 10 13:37:39 2024 -0400 bump LT revision commit 04347e67c6f87ee7a33c8ed8103aecebac6c3888 Author: Jean-Marc Valin <[email protected]> Date: Wed Apr 10 02:02:59 2024 -0400 Missing blockquotes commit acb7e0012ed6d9ec95604160591978dd7c3a9590 Author: Jean-Marc Valin <[email protected]> Date: Wed Apr 10 02:01:40 2024 -0400 FARGAN instructions commit fdb198e88660721e289df94c29e91f70caff787e Author: Jean-Marc Valin <[email protected]> Date: Tue Apr 9 14:29:12 2024 -0400 dump_data: remove all noise and output one signal Now used for fargan instead of LPCNet commit 4c5c498825f9442fb93f2ae902bcbc2e79e46072 Author: Jean-Marc Valin <[email protected]> Date: Tue Apr 9 13:53:20 2024 -0400 rename lpcnet_demo to fargan_demo commit 504566f35a7fd4efc7a242bc7f699ef930b87f02 Author: Jean-Marc Valin <[email protected]> Date: Tue Apr 9 13:40:11 2024 -0400 matching types commit 6ba257d8195039f25000b5b3a21a0a017ad70e8d Author: dvosully <[email protected]> Date: Fri Apr 5 18:30:02 2024 +1000 Change type of function parameter to match implementation Signed-off-by: Jean-Marc Valin <[email protected]> commit cbeebf007b8bed199212cb4e5da5ae79a5b24f97 Author: Malcolm Nixon <[email protected]> Date: Wed Apr 3 22:50:33 2024 -0400 Update cmake to 3.16 and add OPUS_STATIC_RUNTIME option to control MSVC runtime library choice. Signed-off-by: Jean-Marc Valin <[email protected]> commit 0e30966b198ad28943799eaf5b3b08100b6f70c3 Author: Jean-Marc Valin <[email protected]> Date: Mon Apr 1 04:03:46 2024 -0400 Adding more context for PLC Should fix the few cases where the PLC would create voice frames that shouldn't be there. commit 95dbea83486b90256785aa3c75dd2827f591a34c Author: Marcus Asteborg <[email protected]> Date: Thu Jun 22 16:46:50 2023 -0700 Script to build Autotools, CMake and Meson Signed-off-by: Jean-Marc Valin <[email protected]> commit fa9c1e715e6edd0576ec3d4e5c3c29499b3b1db9 Author: Thomas Daede <[email protected]> Date: Wed Mar 1 00:40:37 2023 -0800 Update Opus in ISOBMFF spec to version 1.0.0. The version in the most recent draft has shipped in Firefox, Chromium, and FFmpeg for several years and is quite stable. Normally we would consider bumping the version field for the dOps box, however as far as I know no incompatible version of the box has ever been deployed, so I propose leaving it as is. Signed-off-by: Jean-Marc Valin <[email protected]> commit 12239ced101ffee481781a2eb3b8c88bea523085 Author: Jean-Marc Valin <[email protected]> Date: Thu Mar 14 15:17:33 2024 -0400 renaming DNN options in meson commit ca901e65aab8d4b5b85d2cb2649819c24e0b1602 Author: Xavier Claessens <[email protected]> Date: Tue Jun 20 08:18:00 2023 -0400 meson: Use pkgconfig generator It is much less error prone because Meson can detect dependencies automatically. As bonus Meson will also generate the opus-uninstalled.pc file. Signed-off-by: Jean-Marc Valin <[email protected]> commit e7d4e82bc065747d94829d93cc9d8a9d1eab7951 Author: Timothy B. Terriberry <[email protected]> Date: Thu Mar 14 08:00:53 2024 -0700 Fix _mm_loadu_si32 detection for vendored Clang. Apple uses different __clang_major__ version numbers than upstream, so our test did not work. This caused compilation failures with, e.g., XCode 10.1, which reports __clang_major__ as 10 despite being forked from upstream's 7.0 branch. Fixes #2369 Signed-off-by: Jean-Marc Valin <[email protected]> commit 556c2d446b396cff11987ac1b74ed7bbf0297d78 Author: Jean-Marc Valin <[email protected]> Date: Wed Mar 13 15:11:08 2024 -0400 Adding MSVC AVX2 support for meson build Extracted from this MR from Marcus Asteborg: https://gitlab.xiph.org/xiph/opus/-/merge_requests/82/ commit d7fab5e89289b28e1055d10f348f6d358fa84a00 Author: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com> Date: Fri Feb 2 05:38:59 2024 +0000 Bump gitpython from 3.1.36 to 3.1.41 in /dnn/torch/osce Bumps [gitpython](https://github.com/gitpython-developers/GitPython) from 3.1.36 to 3.1.41. - [Release notes](https://github.com/gitpython-developers/GitPython/releases) - [Changelog](https://github.com/gitpython-developers/GitPython/blob/main/CHANGES) - [Commits](https://github.com/gitpython-developers/GitPython/compare/3.1.36...3.1.41) Signed-off-by: Jean-Marc Valin <[email protected]> commit 84a85e9e63ea687544375fbed3100051249a033b Author: Jean-Marc Valin <[email protected]> Date: Tue Mar 12 02:03:22 2024 -0400 Fix meson AVX2 fixed-point commit a8e4ebb550dbdbb6149ad02d390c34442c8db951 Author: Rudi Heitbaum <[email protected]> Date: Sat Mar 9 18:55:53 2024 +0000 Add OPUS_ARM_INLINE_DOTPROD dotprod check fixes: ../meson.build:322:9: ERROR: Unknown variable "opus_arm_may_have_dotprod" after: dotprod check passes through. Checking if "compiler supports gcc-style inline assembly" compiles: YES Checking if "assembler supports EDSP instructions on ARM" compiles: YES Checking if "assembler supports ARMv6 media instructions on ARM" compiles: YES Checking if "assembler supports NEON instructions on ARM" compiles: YES Checking if "assembler supports DOTPROD instructions on ARM" compiles: NO Program perl found: YES (/usr/bin/perl) Fetching value of define "__APPLE__" : (undefined) Checking if "compiler supports ARMv7/AArch64 NEON intrinsics" : links: YES Checking if "compiler supports AArch64 NEON intrinsics" : links: NO Checking if "compiler supports AArch64 NEON intrinsics with -mfpu=neon" : links: NO Message: Compiler does not support AArch64 NEON intrinsics Checking if "compiler supports AArch64 DOTPROD intrinsics" : links: NO Checking if "compiler supports AArch64 DOTPROD intrinsics with -march=armv8.2-a+dotprod" : links: NO Message: Compiler does not support AArch64 DOTPROD intrinsics refer: - https://community.arm.com/arm-community-blogs/b/tools-software-ides-blog/posts/exploring-the-arm-dot-product-instructions test with: armv7ve-none-linux-gnueabihf-gcc test.c /tmp/cc02sooK.s: Assembler messages: /tmp/cc02sooK.s:32: Error: bad instruction `udot v0.4s,v1.16b,v2.16b' aarch64-none-linux-gnu-gcc test.c /tmp/ccnVi9Ec.s: Assembler messages: /tmp/ccnVi9Ec.s:12: Error: selected processor does not support `udot v0.4s,v1.16b,v2.16b' aarch64-none-linux-gnu-gcc -march=armv8.2-a+dotprod test.c Signed-off-by: Rudi Heitbaum <[email protected]> Signed-off-by: Jean-Marc Valin <[email protected]> commit e2d01822e569f8a7865964f6aa56cf2f81d088bf Author: Rudi Heitbaum <[email protected]> Date: Sat Mar 9 17:58:18 2024 +0000 use semicolon not newline for inline assembler fixes: testfile.c:3:11: warning: missing terminating " character 3 | __asm__(".arch armv5te | ^ testfile.c:4:1: error: expected string literal before '.' token 4 | .object_arch armv4t | ^ testfile.c:5:14: warning: missing terminating " character 5 | qadd r3,r3,r3"); | ^ Signed-off-by: Rudi Heitbaum <[email protected]> Signed-off-by: Jean-Marc Valin <[email protected]> commit 8c439da4eadb59afb704b97e12bfab45fc802698 Author: Rudi Heitbaum <[email protected]> Date: Sat Mar 9 17:39:20 2024 +0000 Extended asm with C operands doesn’t work at top level fix the following test in the meson.build stderr: testfile.c:6:34: error: expected ')' before '::' token 6 |__asm__ (""::) | ~ ^~ | ) testfile.c:6:37: error: expected ';' at end of input 6 |__asm__ (""::) | ^ | ; ----------- Checking if "compiler supports gcc-style inline assembly" compiles: NO refer: - https://gcc.gnu.org/bugzilla/show_bug.cgi?id=41045 Signed-off-by: Rudi Heitbaum <[email protected]> Signed-off-by: Jean-Marc Valin <[email protected]> commit 49d4effeea9107d18f6897255139d30fc80204df Author: Rudi Heitbaum <[email protected]> Date: Wed Mar 6 11:21:07 2024 +0000 fix arm asm meson source build meson does mot support output with paths; add a meson.build file in the arm directory. The output files were being incorrectly placed in the celt/ directory. Program arm/arm2gnu.pl found: YES (/var/media/DATA/home-rudi/LibreELEC.kernel11/build.LibreELEC-H3.arm-12.0-devel/build/opus-v1.5.1/celt/arm/arm2gnu.pl) Configuring celt_pitch_xcorr_arm-gnu.S with command ../celt/meson.build:51:25: ERROR: configure_file keyword argument "output" Output 'arm/armopts.s' must not contain a path segment. before: celt/celt_pitch_xcorr_arm-gnu.S after: celt/arm/celt_pitch_xcorr_arm-gnu.S celt/arm/armopts.s celt/arm/armopts-gnu.S Signed-off-by: Rudi Heitbaum <[email protected]> Signed-off-by: Jean-Marc Valin <[email protected]> commit fcecf9970b242dfa73213e6d00ce9d57979e5fb0 Author: Jean-Marc Valin <[email protected]> Date: Fri Mar 8 23:57:12 2024 -0500 Remove the use of __m128i_u entirely It's just an internal gcc/clang type commit 48a9da08807277e3e78cdbffff0da0a2fc7384da Author: Timothy B. Terriberry <[email protected]> Date: Sun Mar 10 10:28:58 2024 -0700 Add Arm RTCD for FreeBSD. Thanks to Robert Clausecker <[email protected]> for the patch. commit 92e4080c9170e34d4e349bc78e47e5d8b61f8c52 Author: Timothy B. Terriberry <[email protected]> Date: Sun Mar 10 10:26:35 2024 -0700 Make opus_cpu_capabilities() static. The MSVC implementations already was, but the others were not. This is an implementation detail that should not have external visibility. The public interface is opus_select_arch(). commit 824f1becb09e66d2e38d7b5afeae89f4cec993d0 Author: Jean-Marc Valin <[email protected]> Date: Fri Mar 8 23:28:48 2024 -0500 Fix unaligned load with MSVC MSVC doesn't have a real __m128i_u, so it would generate an aligned store, resulting in a segfault. Adding explicit loadu/stureu intrinsics to make sure the compiler generates unaligned load/store commit c64ad657abf4d9f641a3d00cf83b987c55b00d02 Author: Tristan Matthews <[email protected]> Date: Thu Mar 7 14:19:47 2024 -0500 autootools: include all referenced READMEs These were not being included in the tarball in spite of being referenced. Signed-off-by: Jean-Marc Valin <[email protected]> commit cb1956d1fe29ae6a4c320d8f7a7fe35fd69adec8 Author: Jan Buethe <[email protected]> Date: Thu Mar 7 15:15:37 2024 +0100 added list of training/validation files used for osce training commit c1f0f54018bf1f6f86710be1517313fb7b49556c Author: Martin Storsjo <[email protected]> Date: Tue Mar 5 09:11:30 2024 -0500 dnn: vec_neon: avoid redefinition of vcvtnq_s32_f32 clang exposes this intrinsic even in 32-bit mode, if targeting >= armv8, whereas gcc does not, see: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=95399 Signed-off-by: Jean-Marc Valin <[email protected]> commit ab4e83598e7fc8b2ce82dc633a0fc0c452b629aa Author: Tristan Matthews <[email protected]> Date: Mon Mar 4 11:34:31 2024 -0500 autotools: include dnn/meson.build in tarball commit 23d4b31de15a723716f9fde5ec736773f2e1aa2e Author: Jean-Marc Valin <[email protected]> Date: Mon Mar 4 01:42:20 2024 -0500 Fix opus_demo -e/-d with weights blob commit 1bb6d7899721f387255c62b12b2abf64f81a55ce Author: Sid Rao <[email protected]> Date: Sun Mar 3 18:31:32 2024 -0500 Update README for 1.5 commit 0ff629bf9706b016c0622a188ed8710b7a051cab Author: Jean-Marc Valin <[email protected]> Date: Sun Mar 3 13:16:49 2024 -0500 Fix configure help for --enable-osce commit 4eca11c001294a2495f405773795b6d919605ca5 Author: Jean-Marc Valin <[email protected]> Date: Sun Mar 3 02:55:37 2024 -0500 Avoid OSCE crash if weights aren't loaded commit 32d4d874accd322f7e237b734678542fea88393b Author: Jean-Marc Valin <[email protected]> Date: Sun Mar 3 02:45:39 2024 -0500 Basic void pointer check Only manage to warn on non-pointers commit 33a89b7ea8db4d9a6fcc802aa85264e13a4ebbaf Author: Jean-Marc Valin <[email protected]> Date: Sun Mar 3 00:14:55 2024 -0500 Add checks when loading blob data commit c9276272abc65b2a06d13d1b351d2c52417270d9 Author: Jean-Marc Valin <[email protected]> Date: Sat Mar 2 17:38:03 2024 -0500 missing newlines commit efeaa8aef8ba3a29fbba04908ce61ebb8e225fd1 Author: Jean-Marc Valin <[email protected]> Date: Sat Mar 2 17:36:09 2024 -0500 Make weights blob a void* commit 24b7eab4a30bd4fb3769fc532ab0d8af379c255d Author: Jean-Marc Valin <[email protected]> Date: Sat Mar 2 14:42:07 2024 -0500 Bump LT version Many new features, API still compatible commit b4ff554268a6edaf154f01c646ae528cab0dcd58 Author: Jean-Marc Valin <[email protected]> Date: Sat Mar 2 15:04:20 2024 -0500 Fix conversion warnings commit 1f5189a50a41a07ebc15f0d3423ef236de9f9893 Author: Jean-Marc Valin <[email protected]> Date: Sat Mar 2 14:38:34 2024 -0500 Actually use RTCD in the PLC feature prediction commit 6880cddec1a48c018511820929ad9d11ae23105a Author: Jean-Marc Valin <[email protected]> Date: Sat Mar 2 00:33:48 2024 -0500 Fix clang alignment warning commit ab2ab570946e5d15b16491219f23a05446f628c3 Author: Jean-Marc Valin <[email protected]> Date: Fri Mar 1 23:49:29 2024 -0500 Fix NaN in Deep PLC silk_burg_analysis() could return a slightly negative value on zero input, which would cause a negative, which the log didn't like. commit 5c8576383b7613dc8ff3d69dd435e56811da82ed Author: Jean-Marc Valin <[email protected]> Date: Fri Mar 1 19:16:31 2024 -0500 Fixes ubsan tests with clang Without the fix, ubsan would complain about some of the NULL pointer checks from test_opus_api. commit bd3ce03103be4d98489d90f2f8c089edbb13bdc1 Author: Jean-Marc Valin <[email protected]> Date: Fri Mar 1 17:43:08 2024 -0500 Avoid warning about LPCNetPLCState being redefined commit 0713a18ebc87bad579b901b3dcd2499d8e5b552b Author: Jean-Marc Valin <[email protected]> Date: Fri Mar 1 17:34:52 2024 -0500 Fix overflow in CELT Deep PLC Added proper saturation and rounding commit e9b243b32a7d2e85b0dcfb9704c507bb59f8a3cf Author: Michael Klingbeil <[email protected]> Date: Thu Feb 29 16:13:46 2024 -0500 add arm rtcd for apple Signed-off-by: Jean-Marc Valin <[email protected]> commit b6fd9aaa0da2a700c2d0dca87f9fe6e02d4a94e8 Author: Jean-Marc Valin <[email protected]> Date: Thu Feb 29 22:32:01 2024 -0500 Allow wrap-around in Neon NSQ_del_dec LCG Matches the C code and avoids undefined behaviour commit 26c3bbbe8f58c233714efae9cd758104c8de938e Author: Rudi Heitbaum <[email protected]> Date: Mon Aug 21 19:46:18 2023 +1000 meson fix comparison cc.get_define returns str (not bool) Fixes: Fetching value of define "__APPLE__" : ../meson.build:316:12: ERROR: Object <[StringHolder] holds [str]: ''> of type str does not support the `bool()` operator. Signed-off-by: Jean-Marc Valin <[email protected]> commit 23c591318e63f9f38a2d60b361230f148e29fb70 Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 27 14:30:31 2024 -0500 Remove NORM_ALIASING_HACK (with SMALL_FOOTPRINT) It was breaking badly for PLC. commit 91bfdbd40ffcc9402cdbbefa7e3a1bd8cf3760e6 Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 27 12:40:36 2024 -0500 Fix lpcnet_demo usage -fargan-synthesis not -fargan_synthesis commit 1fc28c3830d53f645a855c7f223536aa6d1be594 Author: Jean-Marc Valin <[email protected]> Date: Mon Feb 26 12:43:39 2024 -0500 Allow band boost in dynalloc_analysis() for 2.5 ms Used to be disabled for LM==0 because of the unreliable energy in one-bin bands. Now we just used the max with the previous energy to stabilize things. commit 448518fbedf7d9c752ad2dfb855c1286fbc31797 Author: Jean-Marc Valin <[email protected]> Date: Sun Feb 25 17:14:29 2024 -0500 Add some DRED decoding tests commit c0cc80dcf4d59b554b55be40dcebfcc00ddc83dd Author: Jean-Marc Valin <[email protected]> Date: Sun Feb 25 13:35:42 2024 -0500 s/master/main/ in gitlab script commit dcce2fd455b1f407bf4e1347ce5358a6d0096bd2 Author: Jean-Marc Valin <[email protected]> Date: Sat Feb 24 23:37:44 2024 -0500 Move all DRED encoding/decoding files to dnn/ dir commit b589ab470add6e376a1ed4d72934fb74ee3636cc Author: Jean-Marc Valin <[email protected]> Date: Sat Feb 24 23:29:12 2024 -0500 Silence warning about uninitialized float_api commit 522a29057102ab853e5b0bb47602e787cd5ff65a Author: Jean-Marc Valin <[email protected]> Date: Sat Feb 24 03:41:47 2024 -0500 _mm_loadu_si23() needs immintrin.h on MSVC commit 4c7602972220f9f59b153c800c86e03b771b781f Author: Jean-Marc Valin <[email protected]> Date: Fri Feb 23 16:15:11 2024 -0500 Fixing Neon when vmlaq_lane_f32() is a macro commit a17c2948a0ea0a310511f65ec0c81d907dfdc15d Author: Michael Klingbeil <[email protected]> Date: Fri Feb 23 11:56:13 2024 -0500 add usage string for opus_demo dec_complexity Signed-off-by: Jean-Marc Valin <[email protected]> commit 59dc75fa9713d6543bbb85fe83cb56555513a4de Author: Timothy B. Terriberry <[email protected]> Date: Thu Feb 22 05:48:18 2024 -0800 Rework 32-bit SSE loads yet again. The existing code in vec_avx.h produced warning: dereferencing type-punned pointer will break strict-aliasing rules with gcc 6.4.0. We already had a macro to work around this within the rules of the C standard, but trying to use that here does not get optimized into a single MOVD like we were hoping. Replacing it with memcpy() instead does get optimized correctly, but requires switching from a macro to an inline function in order to be able to declare a local variable and return a value. We already have such an inline function in NSQ_del_dec_avx2.c, so hoist that out and use it everywhere, and then convert vec_avx.h to use it also. commit 1186fb8ea4f977f5d1d0816a7bc8384978966304 Author: Jean-Marc Valin <[email protected]> Date: Fri Feb 23 01:53:48 2024 -0500 Add Deep PLC/DRED/OSCE to random tests Also, remove -march=native because of AVX512VNNI and valgrind commit 6673e34b6566edcb825976ffc178938bbdcbf2ab Author: Jean-Marc Valin <[email protected]> Date: Thu Feb 22 17:56:12 2024 -0500 Fix build on ARMv7 Fixes regression in 83368e6. vcgez_s16() is A64-only, but vcge_s16(..., vdup_n_s16(0)) works everywhere. commit f1fc944b41e9267c021a77a1707528c3ae4b3e3b Author: Jean-Marc Valin <[email protected]> Date: Thu Feb 22 17:27:46 2024 -0500 Fix AVX2 dection broken in 9cf12e9 commit cf4e3a15a382bae17d59224f57fdc3cdf9ba6d44 Author: Jean-Marc Valin <[email protected]> Date: Thu Feb 22 16:19:02 2024 -0500 Bump DRED experimental version for 3e2a6b6 commit 3e2a6b6253fe7a514c50100e4144c52c065a7fa1 Author: Timothy B. Terriberry <[email protected]> Date: Thu Feb 22 06:12:55 2024 -0800 Add signaling for a maximum DRED quantizer. Since any value of dQ > 0 will cause the initial quantizer to degrade to the format-implied maximum (15) with a sufficient number of DRED frames, allow signaling a maximum smaller than 15. This allows encoders to improve the minimum quality of long DRED sequences (at the expense of bitrate) without requiring a constant quantizer for all frames (dQ == 0). commit 2fff6437763d5f1ea42ed1ed1bd8bf6e50643291 Author: Timothy B. Terriberry <[email protected]> Date: Thu Feb 22 06:12:26 2024 -0800 Fix Doxygen warnings. commit 950d8bf15893166fdd99ad0e85a4d1767cbb6b95 Author: Timothy B. Terriberry <[email protected]> Date: Thu Feb 22 04:55:29 2024 -0800 Remove some dead code. commit 9cf12e92bbd25b2416b340b06090efbde9ad3fa6 Author: Timothy B. Terriberry <[email protected]> Date: Thu Feb 22 04:49:51 2024 -0800 Improve AVX2 compiler support detection. Commit 735c40706f37 added uses of intrinsics that require at least gcc 9.0 (cf. <https://gcc.gnu.org/bugzilla/show_bug.cgi?id=78782>), even though AVX2 support may appear to be available in earlier gcc versions. We were not testing for this. Update the compiler test in configure.ac to use these intrinsics explicitly, so it will error out and disable AVX2 if they are not available. commit 833688e65dda31b6cfc319b5dcd0a54f3a2ef616 Author: Jan Buethe <[email protected]> Date: Wed Feb 21 17:27:54 2024 +0100 bit-exact overflow fixes in silk/arm/NSQ_del_dec_neon_intr.c commit 57901a6758c3bdc7481d61669812bde13d2085b8 Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 20 20:54:13 2024 -0500 opus_dred_parse() sets dred_end to 0 when no DRED Also, fix documentation about return value of zero. commit 6ac0c87112804e963d28cd1ff6510e80b210de4c Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 20 17:49:13 2024 -0500 Update weight-shrinking script commit d9d0e7292f9024b94d88f5d7b29b8bec4441fe0b Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 20 14:23:59 2024 -0500 Fixes an aliasing bug in opus_packet_pad() Trying to add padding in-place breaks when we have extensions, which causes a memcpy() with overlapping data. Just doing a copy instead. commit ecc10d835d4e2c2e7a21c91e980828c30728763a Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 20 14:18:41 2024 -0500 Add missing RESTORE_STACK in tests Silences NONTHREADSAFE_PSEUDOSTACK warnings commit 001820bbdef35783da5afd68ca98fcf524b17706 Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 20 14:13:17 2024 -0500 Fix NONTHREADSAFE_PSEUDOSTACK commit 512e6270ea316b5a07656b060419a38c1e5a818f Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 20 14:11:57 2024 -0500 Silences gcc warning warning: expression does not compute the number of elements in this array Seems like gcc thinks we're trying to get the number of elements in our array or something like that. It then suggests adding parentheses to silence the warning. commit b75bd48d82281193681c49c00fca9773a45fb0d8 Author: Jean-Marc Valin <[email protected]> Date: Sun Feb 18 16:36:04 2024 -0500 Remove training whitespace commit 5eeb5766718c32db20680cfc5ce7cee068df84f3 Author: Jean-Marc Valin <[email protected]> Date: Sun Feb 18 13:57:18 2024 -0500 Instructions for reusing loss simulator commit 393d463fdd6d17f3fef126a019102694ad89e2f7 Author: Jean-Marc Valin <[email protected]> Date: Sat Feb 17 14:20:44 2024 -0500 Add lossgen_demo Also skip the first loss values being generated since they're biased towards "not lost" due to the initialization. commit a97151d390978d93b4311ef8794bd3af23703355 Author: Xavier Claessens <[email protected]> Date: Fri Feb 16 18:18:35 2024 -0500 meson: Increase slow tests timeout They timeout on GitHub actions because those runners are slower. commit 8894546bed8a58f43f92bffc2c80fd82485b2750 Author: Giovanni Bajo <[email protected]> Date: Fri Dec 29 12:06:40 2023 +0100 dump_modes: add missing file to build Signed-off-by: Jean-Marc Valin <[email protected]> commit 5e0bb53e096101a2afe7c5f6435825b07d87f45b Author: Chris Hold <[email protected]> Date: Thu Feb 15 15:06:40 2024 +0200 Map 2 extra channels in 5th order HOA Signed-off-by: Jean-Marc Valin <[email protected]> commit 965afac29b33465c53b4b98b07aa350322af16ea Author: Chris Hold <[email protected]> Date: Thu Feb 15 14:42:53 2024 +0200 Provide 4th order HOA map 3 mixing and demixing Signed-off-by: Jean-Marc Valin <[email protected]> commit befc25fb766be73e360d4a9482fc13e0360f616c Author: Jan Buethe <[email protected]> Date: Fri Feb 16 18:51:29 2024 +0100 fixed compiler warning when building without dred commit db78df8c01d386ef1fff9c99d38f9f44f726cb9f Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 6 22:11:49 2024 -0500 Delaying new DRED data when just out of silence We don't need redundancy for the first active frame since we already have the main Opus payload. commit c5117c5ccd5da2680b29dbdae5d648d750107003 Author: Jean-Marc Valin <[email protected]> Date: Mon Feb 5 17:39:38 2024 -0500 Add dred_end return value to opus_dred_parse() commit 1f53f1e0a9b1e055222b28a70b2e327787e50d09 Author: Jean-Marc Valin <[email protected]> Date: Mon Feb 5 14:24:02 2024 -0500 Support for extra offset Allows us to exclude the most recent silence from DRED commit 183a820212381f6c447b5a7c9b92b34fa01c629b Author: Jean-Marc Valin <[email protected]> Date: Sat Feb 3 02:51:08 2024 -0500 Refactoring: store all states commit 9f36bfc9623d0af495913b073a0b5e9e627e3086 Author: Jean-Marc Valin <[email protected]> Date: Fri Feb 2 16:55:21 2024 -0500 Chopping the oldest silence in a DRED payload commit 9b1da1fb1f07265dda3621b30ea989911dd4f0bf Author: Jean-Marc Valin <[email protected]> Date: Thu Feb 15 18:05:07 2024 -0500 Fix missing dotprod optimization Use the neon version of silk_noise_shape_quantizer_short_prediction() commit 367a487e7cec832ccd4ab2d132e723b23336758b Author: Jan Buethe <[email protected]> Date: Thu Feb 15 15:39:30 2024 +0100 hangover fix in osce/utils/pitch.py commit 46f9c9c6698f64a9e63a68dcc507042322bd3df9 Author: Jan Buethe <[email protected]> Date: Thu Feb 15 15:30:04 2024 +0100 re-dumped osce models with sparse=False commit 735117b6d7697312962e99597eb516fbb3cc8360 Author: Jan Buethe <[email protected]> Date: Thu Feb 15 15:25:06 2024 +0100 disabled sparse option in osce export script commit ffd1b0b137e82197f8f995e03763a65b36079eba Author: Chris Hold <[email protected]> Date: Thu Jan 11 17:10:22 2024 +0200 Provide 5th order HOA map 3 mixing and demixing Signed-off-by: Jean-Marc Valin <[email protected]> commit 6be3673c225795de83849fbeed2c514377efd722 Author: Jean-Marc Valin <[email protected]> Date: Wed Feb 14 17:35:29 2024 -0500 More #ifdef around the dnn code commit 901c8548af2b3606207f8c41bf08946659c06720 Author: Jean-Marc Valin <[email protected]> Date: Wed Feb 14 11:51:44 2024 -0500 Conditional include Thanks to Igor Palaguta for reporting the issue. https://github.com/xiph/opus/issues/313 commit dd0e2dc3391ae20a1c05c91a5ee5d4179e27062f Author: Jan Buethe <[email protected]> Date: Wed Feb 14 10:37:15 2024 +0100 updated model commit 4b9d9b0030d3103b9f19d32935ddd3a90f2305a9 Author: Jean-Marc Valin <[email protected]> Date: Sun Feb 11 14:04:43 2024 -0500 Fix check-asm for celt_fir_sse4_1() commit 3e69410e29b0cc4e8a6e9712d7c980d702597d62 Author: Timothy B. Terriberry <[email protected]> Date: Fri Feb 9 16:42:15 2024 -0500 Fix OOB read in fixed-point NEON intrinsics. xcorr_kernel_neon_fixed() read one more sample from y[] in the main loop than it needed to allow use of vector loads, but unlike the native asm in celt_pitch_xcorr_arm.s, the loop condition did not exit early enough to prevent this from overrunning the end of the array. Additionally, the tail loop _always_ read one value beyond what it needed. This patch fixes the loop condition on the main loop. Since this makes the tail section run even for lengths that are a multiple of 8 (e.g., on fully half the multiplies for usages like celt_fir() or celt_iir() with an order of 16, which is common), rather than try to fix the tail loop, we replace it with a non-looping adaptation of the native asm, which continues to use vector loads as much as possible for the remaining elements (and also does not read ahead past the end of the y[] array). Overall slowdown of test_opus_encode on a Raspberry Pi 5 Model B Rev 1.0 is 0.12% vs. 0.13% for fixing the existing tail loop. Signed-off-by: Jean-Marc Valin <[email protected]> commit d503125101116d2b399287824d7902b6351b691d Author: Timothy B. Terriberry <[email protected]> Date: Fri Feb 9 17:26:35 2024 -0500 Add check-asm for fixed-point xcorr_kernel(). Compare the output of xcorr_kernel() against the results of xcorr_kernel_c() when configured with --enable-check-asm. Currently this is only checked in fixed point, as a float check requires more sophisticated error analysis and may need to be customized for each vector implementation. Signed-off-by: Jean-Marc Valin <[email protected]> commit 65b131ec0984973166973878b14506f782704a3f Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 6 20:52:21 2024 -0500 Add basic testing for Deep PLC, DRED, and OSCE Still need more targeted tests, DRED decoding commit 7070dfec4f473f54d588827871fe386cbd06470a Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 6 19:48:29 2024 -0500 Make opus_packet_unpad() discard extensions too Same for opus_multistream_packet_unpad() commit 17922c2a28ea97b2e90e1493123facb0d26c46b5 Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 6 15:48:21 2024 -0500 Fix internal error on DRED Forgot to account for padding length bytes when DRED payload is large. commit 562587e91b5ff5534a4b22a1adab7329c6c62670 Author: Jean-Marc Valin <[email protected]> Date: Tue Feb 6 15:38:50 2024 -0500 Avoid size-zero OPUS_COPY() with NULL pointer Fails ubsan because memcpy declares args as non-null commit 2582ca925988cd53edf0c4d6690dba2c66fde8e8 Author: Jean-Marc Valin <[email protected]> Date: Fri Feb 2 18:32:55 2024 -0500 Allow wrap-around in silk_LPC_analysis_filter_avx2() Matches the C version (see 4a7027b) commit e12c7f584a542ec6f2b00be67bf33165e182b24b Author: Jean-Marc Valin <[email protected]> Date: Fri Feb 2 15:07:01 2024 -0500 Fix log(0) on silence for fixed-point commit 0e2d56d6750209a777c1b76cc75dbff37cda1a95 Author: Jean-Marc Valin <[email protected]> Date: Fri Feb 2 14:46:51 2024 -0500 Add missing NULL pointer check commit 009d7412e1b374ccdd542aff5fe9becfde6d941e Author: luzpaz <[email protected]> Date: Fri Jul 21 16:19:29 2023 +0000 Fix various typos Found using `codespell -q 3 -L caf,highe,inlin,nd,ordert,shft` Signed-off-by: Jean-Marc Valin <[email protected]> commit f20575dd8632d371a51478ff55996d4ecc35ff1e Author: Jean-Marc Valin <[email protected]> Date: Wed Jan 31 21:52:08 2024 -0500 Fix OSCE using uninitialized range coder for PLC commit 53c2313c5876539ae147a5135421cf10f56d6404 Author: Jean-Marc Valin <[email protected]> Date: Wed Jan 31 18:30:28 2024 -0500 Fix lossgen shared build commit 6c8acc21dda42573be4812d2fe97d24adc887c74 Author: Jean-Marc Valin <[email protected]> Date: Wed Jan 31 13:08:37 2024 -0500 Avoid padding multi-frame DTX packets commit 648a9f24b425e6851566d2461e1f9187efb72fce Author: Jean-Marc Valin <[email protected]> Date: Wed Jan 31 13:07:51 2024 -0500 Allow for DRED in DTX refresh packets commit 4350819785bd16c6fd30100366001f19d5807d03 Author: Jean-Marc Valin <[email protected]> Date: Wed Jan 31 12:59:08 2024 -0500 Handle the offset from the DRED frame id commit f4ee2925f65c0cf73f0f5bb80b915181675f474c Author: Jean-Marc Valin <[email protected]> Date: Wed Jan 31 00:02:57 2024 -0500 Fix frame separator parsing commit 0fed741a87ccc061eff382d306fadd71acdfc57d Author: Jean-Marc Valin <[email protected]> Date: Tue Jan 30 21:53:58 2024 -0500 Fix c90 build commit 468a693dd44cee8bb883766e5f623c24fbda2735 Author: Jean-Marc Valin <[email protected]> Date: Sun Jan 21 14:10:27 2024 -0500 Cleanup previous commits Rename, reindent, change arg order commit b778271d53928445964cfe801d7461e6db7a67fa Author: Jean-Marc Valin <[email protected]> Date: Sat Dec 16 13:01:20 2023 -0500 divide max payload too commit 073bec9160f6c39fef22eb0442ab6999ce822ffb Author: Jean-Marc Valin <[email protected]> Date: Sat Dec 16 03:52:20 2023 -0500 First shot at multi-frame CBR with DRED commit fe86db66f47ba8d5d1b4f65f604e49852bbac90c Author: Jean-Marc Valin <[email protected]> Date: Sun Dec 17 19:03:22 2023 -0500 More activity handling to opus_encode_native_process() commit 452abeeac9dc11d7e9073ecc31646fcf5eb066a0 Author: Jean-Marc Valin <[email protected]> Date: Sun Dec 17 18:49:08 2023 -0500 Handle rangeFinal, delay_compensation commit fd88e22391220bdbf5ac86c4b4690cd4e5c46c53 Author: Jean-Marc Valin <[email protected]> Date: Sat Dec 16 01:54:09 2023 -0500 Refactor multi-frame encoding to be non-recursive commit f44069f58be251402afc321f773002e2dde6a94f Author: Jean-Marc Valin <[email protected]> Date: Fri Dec 15 17:48:54 2023 -0500 Splitting opus_encode_native() commit 231caa372034aaa51c40f643b571635fecc2645e Author: Jean-Marc Valin <[email protected]> Date: Tue Dec 19 22:12:03 2023 -0500 Fix Hybrid CBR with DRED and CELT->SILK redundancy Need to move the redundant frame even in CBR because the hybrid frame now gets encoded as VBR, with DRED picking up the rest. Fixes an issue introduced in 4600e77. commit b63e22cff9601ab2249ce5b6371a5ca9e663ce09 Author: Jean-Marc Valin <[email protected]> Date: Tue Dec 19 01:55:28 2023 -0500 Fix desync for CBR DRED The encoder wouldn't reserve enough bits for CELT, causing it to not have enough bits to code the switching redundancy flag when it should have. commit 7b73c9bc7ff8e54bb6b72aad500bdab5d031aee0 Author: Jean-Marc Valin <[email protected]> Date: Tue Jan 23 19:22:05 2024 -0500 More DRED tuning commit 19dd96b3fa02b7f9d0817770c4b42879d23d048d Author: Jean-Marc Valin <[email protected]> Date: Mon Jan 22 03:29:37 2024 -0500 Initial DRED tuning Adjust q0, qD and duration based on bitrate and loss. commit 7df2c67be1a976cf10b7094b289180b1b5bb1c94 Author: Jan Buethe <[email protected]> Date: Tue Jan 23 17:10:34 2024 +0100 fixes in osce python code commit 3499d0aac76d20ba14918cafb8020278154bf2e6 Author: Jan Buethe <[email protected]> Date: Mon Jan 22 15:23:09 2024 +0100 switched to smaller NoLACE model commit ec04a94eb2000e86b90c186ff56d518c260f2d60 Author: Jan Buethe <[email protected]> Date: Mon Jan 22 15:12:52 2024 +0100 bugfix in SilkFeatureNetPL commit 5f8201c71ee81a9eb7bb302d1bd72fe15678d213 Author: Jan Buethe <[email protected]> Date: Mon Jan 22 15:12:26 2024 +0100 OSCE_MAX_RNN_UNITS now derived from osce model parameters commit 6a9831a6b038638266165dc1e9f115678f0b330e Author: Jean-Marc Valin <[email protected]> Date: Thu Jan 18 18:16:54 2024 -0500 Remove run-time code for old TF2 models No longer needed now that PLC is trained with PyTorch stack commit 1ddfcfd48cb87f8dc29240d705a4da78bae0eb50 Author: Jean-Marc Valin <[email protected]> Date: Wed Jan 17 15:15:22 2024 -0500 Using PyTorch model (same architecture for now) commit e699263660f4b476511be407a5bb6c1b93db59a4 Author: Jean-Marc Valin <[email protected]> Date: Mon Jan 15 18:24:15 2024 -0500 Improving PLC Should handle the history in a more consistent way. Slightly increase the model size and re-enable biased band loss in training. commit 299e38cab774fa4bd9708581210af8b09c6b5e4e Author: Jan Buethe <[email protected]> Date: Mon Dec 18 12:19:55 2023 +0100 Updated LACE and NoLACE models to version 2 commit 4f311a1ad44f1b7bd60e32984ca0604c46b6c593 Author: Jean-Marc Valin <[email protected]> Date: Wed Jan 17 02:26:48 2024 -0500 PLC export script mostly untested commit 26ddfd713537accce773acc12f565021f4f6d28c Author: Jean-Marc Valin <[email protected]> Date: Mon Jan 15 18:10:21 2024 -0500 PyTorch code for training the PLC model Should match the TF2 code, but mostly untested commit 6ad03ae03e3b37dc472c291e4e77997bf64e6965 Author: Jean-Marc Valin <[email protected]> Date: Fri Dec 22 20:14:10 2023 -0500 Prevent overshoots from CELT PLC with prediction Constrains the energy prediction to something safe. commit bd2e9a34fba837386082e5e16f1b878a16f2274e Author: Jean-Marc Valin <[email protected]> Date: Thu Dec 21 23:36:16 2023 -0500 Add simulated loss to opus_demo commit caca188b5a0275b1c04baf8fcc9798b900692a2c Author: Jean-Marc Valin <[email protected]> Date: Thu Dec 21 23:05:40 2023 -0500 Make loss simulator standalone commit bd710e97f31cbd001c7f13e2c5ece01a3ed487d6 Author: Jean-Marc Valin <[email protected]> Date: Thu Dec 21 21:30:53 2023 -0500 C code for packet loss simulator commit b923fd1e2811a4bf6a4ea1461a550c8d15143f01 Author: Jean-Marc Valin <[email protected]> Date: Thu Dec 21 18:01:57 2023 -0500 lossgen: better training, README.md commit c40add59af065f4fdf80048f2dad91d6b4480114 Author: Jean-Marc Valin <[email protected]> Date: Thu Dec 21 16:57:35 2023 -0500 lossgen: can now dump weights commit 627aa7f5b3688ba787c69e55e199ba82e2013be0 Author: Jean-Marc Valin <[email protected]> Date: Thu Dec 21 15:34:33 2023 -0500 Packet loss generation model commit 7d328f5bfaa321d823ff4d11b62d5357c99e0693 Author: Jan Buethe <[email protected]> Date: Wed Nov 8 14:03:39 2023 +0100 Merge LACE/NoLACE under OSCE framework commit 591c8bad70d8aa414729d1a243a6d930f64d6316 Author: Jean-Marc Valin <[email protected]> Date: Sat Dec 16 22:04:47 2023 -0500 Initialize padding pointers to zero Avoids valgrind complaining about use of uninitialized memory commit 12fbd8111a7da79855bdde58cf1f135c94397858 Author: Michael Klingbeil <[email protected]> Date: Fri Dec 15 15:48:58 2023 -0500 use opus_(re)alloc and opus_free for dnn and DRED related functions commit f5a1efdc17aebeb7ee890e207f280f3fe4522ca4 Author: Michael Klingbeil <[email protected]> Date: Wed Dec 13 21:39:57 2023 -0500 handle extensions in opus_repacketizer_out_range_impl commit 6d7ae213ce07cd3090a3d77ad0e79035bcf5d191 Author: Michael Klingbeil <[email protected]> Date: Tue Dec 5 20:43:30 2023 -0500 add extensions of the first frame of a multiframe packet commit f27798da7b09a69c74265654db3509a1573355f4 Author: Jean-Marc Valin <[email protected]> Date: Tue Dec 5 16:58:45 2023 -0500 Fix RESYNTH bit rot commit c7bfc72d072dda08adb4f233a0cf84ee83b3a1a5 Author: Michael Klingbeil <[email protected]> Date: Wed Nov 29 21:40:21 2023 -0500 use vec_avx.h for MSVC builds commit 8090aaca9f38395883c486c28d6bed4bb4e49959 Author: Michael Klingbeil <[email protected]> Date: Wed Nov 29 20:02:27 2023 -0500 don't redefine _mm_loadu_si32 on MSVC commit 88fc293799c851d3c1873e0f98ae0ace0eba88bb Author: Jean-Marc Valin <[email protected]> Date: Wed Nov 29 18:17:30 2023 -0500 Defining __SSEx__ macros when needed for MSVC commit f126bfc531b9bf61fb92af70ee0a138cd7d0f99a Author: Michael Klingbeil <[email protected]> Date: Wed Nov 29 13:38:45 2023 -0500 fix autogen.bat model download commit 0d823c137c5d733a5240ba2055bc38bfd29398d1 Author: Jean-Marc Valin <[email protected]> Date: Wed Nov 29 02:50:24 2023 -0500 Add a script to shrink the DNN models Removes float debug weights, as well as useless spaces commit 443510c2d12e8fff311111e9bfbfe5434ead8616 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 28 23:49:24 2023 -0500 Fix Windows path commit 5578824258c4ceea28b010a60de4a535bb028d87 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 28 23:39:48 2023 -0500 Fix model download path for windows commit ddfa48046bc3af47f4f3e070c64eae4e21ac8f32 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 28 23:32:30 2023 -0500 Opus github ci files Use OPUS_DRED instead of NEURAL_FEC commit 08eefed7cc81c82382c2b7a34e7465868f9da885 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 28 23:18:50 2023 -0500 Add dotprod support to meson Also default to disabling dnn float debugging commit c28b0f10bc6f683ddfb025781960f92d1d3b52e1 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 28 19:14:27 2023 -0500 Trying to fix/update meson build Still don't quite know what I'm doing commit 147b72293f0bc2e3cb17c3f2dc6c21d9d599ec70 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 28 15:34:29 2023 -0500 Oops, fix the fixed-point build commit db26e381a45aadcd82851075b85e2466e7de77d2 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 28 14:16:57 2023 -0500 Trying to use fma instructions when possible Compilers sometimes replace vmlaq*() with fmul+fadd instead of fmla. Trying to use vfmaq*() instead when possible. commit 72cc88dfddce319aeac075bd28eff791cd2b14d8 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 28 04:11:53 2023 -0500 FARGAN model update Finished adversarial training on 800k model. Also, move weights to a new location. commit df637713aac51cb6c14ebfe07fad00819a99401f Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 27 22:57:32 2023 -0500 Fixes for ARMv7/AArch32 1) Enable asm/intrinsics even for floating-point 2) Make sure ARMv8 asimd enables EDSP/MEDIA/Neon 3) Add dotp architecture to rtcd table since AArch *can* have dotp commit c143b72c4c321b5907cbe839079efd3b2455ac9a Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 27 18:08:20 2023 -0500 Enabling DNN optimizations for ARMv7 Adds RTCD tables for compute_activation() and compute_conv2d() commit ee1bb69f2d7c086df72a01632b0563c92896e8b1 Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 27 17:55:27 2023 -0500 Only force auto-vectorization for GCC >= 5.1 commit 7cc30ec6817dec403ec98f1e0da30dfc7473f413 Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 27 16:44:11 2023 -0500 Force vectorization for DNN primitives Avoids having to write intrinsics for simple loops commit d4506af5a9309dda4f798c70ce38dd95632e9b8d Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 27 15:41:41 2023 -0500 Enable floating-point approximations by default Enabling only on platforms that have been tested just in case we run into a non-IEEE754 platform where they would break. commit db6dad446c7d7f97ee3a81e50253fd0459fa99d6 Author: Jean-Marc Valin <[email protected]> Date: Sun Nov 26 22:21:29 2023 -0500 Fix ARMv7 optimizations for DNN code commit cc11c078cd8e1baf642ef0f1d2deaa98af596581 Author: Jean-Marc Valin <[email protected]> Date: Sun Nov 26 03:36:46 2023 -0500 First step towards DNN optimization for ARMv7 Neon Still missing some intrinsics commit c9af8f80f7976a7694c710f1426d816a67364a56 Author: Jean-Marc Valin <[email protected]> Date: Sun Nov 26 03:16:34 2023 -0500 Fix potential read out of bounds in fargan commit 5c3795b2879108f897d465f36885408d5325b77b Author: Jean-Marc Valin <[email protected]> Date: Wed Nov 22 19:05:52 2023 -0500 Adding dotprod instruction to ARM rtcd Used for DNN matrix multiplies commit 984f35b313d57280e3e1b108ba3418e7e6232e22 Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 24 18:28:08 2023 -0500 Speed up cross-correlation normalization commit d65b7de3c559b5f38119ac96838e2716236cd572 Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 24 18:08:01 2023 -0500 Use arch-specific celt_inner_prod() for features commit ddbdbec444b07fc223ecad73e5c2467c2846aec9 Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 24 18:02:35 2023 -0500 Optimize biquad() to reduce dependency chains commit 176507e4fcb4c6376af5ec465f23692ce84495fd Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 24 13:33:04 2023 -0500 Remove process_single_frame() Code moved to compute_frame_features() commit 9d0425d88be5de3278f687f766df1f0b3d14005a Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 24 13:23:52 2023 -0500 Remove feature writing (fwrite()) from libopus commit f5821193e61292280accd10c77fb24bcf6be1fc0 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 21 16:59:28 2023 -0500 Using the same condition for enabling rtcd for cmake, force PRESEUME_SSE4_1 on PRESUME_AVX2 commit 3e18d9675910313a53f94fd454e32a8990107632 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 21 16:13:20 2023 -0500 Trying to fix CMake build aka banging on it until it builds on my machine. Further improvements welcome commit 239d223d84c20d5c146ce6d5200b1b148ab85af6 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 21 02:56:04 2023 -0500 Add rtcd for silk_inner_product_FLP() commit b93e4a149c1bb77e65f4e2c66249553d2a9c4428 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 21 02:13:06 2023 -0500 Start enabling AVX2 silk_inner_product_FLP() Not yet with rtcd commit ed9006038966d8ab059964e9bd4918e8d5180512 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 21 01:26:40 2023 -0500 Avoids AVX2 optimizations being disabled commit c066af1bf155c5157aa67f355d808be119d79fd1 Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 21 01:13:30 2023 -0500 Use SILK VBR when using CBR with DRED DRED will absorb the bitrate variation commit 6f99a3382d241c83a53709ab9dd3308aa11efbb1 Author: Jean-Marc Valin <[email protected]> Date: Sat Nov 18 01:39:42 2023 -0500 Misc fixes on previous patch Fixes warnings, undefined behaviour, and check-asm failure commit 735c40706f37aa5de935f9036c606b2ff39e4f66 Author: Victor Ding <[email protected]> Date: Fri Nov 17 23:58:19 2023 -0500 Optimize NSQ_del_dec() for AVX2 The optimization is bit-exact with C function. This optimization speeds up SILK encoder (floating point) as following: AMD Zen: Complexity 0-5 : 0% Complexity 6-7 : 3 - 7% Complexity 8-10: 8 - 15% Intel Skylake: Complexity 0-5 : 0% Complexity 6-7 : 14 - 18% Complexity 8-10: 17 - 22% Adapted by Jean-Marc Valin commit 452aa95211bfaa0ee8dbf05caa769f2b3a8c7d38 Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 20 17:53:18 2023 -0500 AVX2 version of silk_inner_product_FLP() Not hooked up commit 108512604942682df1b37c4264c13eeeab56ed13 Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 20 16:18:13 2023 -0500 Remove AVX pitch code for fixed-point commit 161358d6c47dd95dea64ebc09500a54024b79d74 Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 20 16:12:46 2023 -0500 Speeding up transient_analysis() Reducing dependency chains commit f42940bef9493bda2be80d363c279b3dbfba2561 Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 20 14:13:23 2023 -0500 Make sure weights files are marked as modified commit d4b04d3275af9938c92a386fc9178977f293362c Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 17 23:10:59 2023 -0500 Speed up silk_warped_autocorrelation_FLP() Reducing the dependency chain between tmp1 and tmp2 at the cost of an extra multiply. commit b2cfd87783713793f4a170bb5a13a1470896436e Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 17 19:36:19 2023 -0500 Add rtcd support for celt_pitch_xcorr_avx2() commit 029385467de35c342d7939196ca2f88cf8998e59 Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 17 18:08:10 2023 -0500 Fix non-RTCD case when SSE is not assumed present Should never occur on amd64, but it could on 32-bit x86 commit 7423ce59e5ac9aebf8ad6d87b268f62461f34afb Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 17 16:59:45 2023 -0500 Use celt_pitch_xcorr_avx2() when guaranteed No RTCD yet commit a93b09e2417ed191d87788d0dbf8b09d053fd59f Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 17 14:14:03 2023 -0500 Adding RTCD for compute_conv2d() commit 91d1f7539ec1a12f6dabc366cec70faac5288b34 Author: Jean-Marc Valin <[email protected]> Date: Thu Nov 16 12:45:50 2023 -0500 FARGAN model update commit 7f7b2a1c662580e214e5fba20eef40816563bfbd Author: Jean-Marc Valin <[email protected]> Date: Wed Nov 15 12:58:52 2023 -0500 Smaller version of fargan 800k parameters, 600 MFLOPS, with a receptive field of 3 feature vectors commit 19a5d6ec03d10920380d5385b7b898e287079a68 Author: Jean-Marc Valin <[email protected]> Date: Thu Nov 16 01:27:40 2023 -0500 Remove C99 comment commit 4bfc0f85553a3dad5393da1b188b9ecf8f44407a Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 14 17:54:05 2023 -0500 Adding RTCD for compute_activation() commit 2e034f6f312d752440b9e26afa82b0752c34d97b Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 13 18:26:31 2023 -0500 Adding RTCD for DNN code Starting with compute_linear() commit b0620c0bf9864d9b18ead6b4bb6e0800542a931d Author: Jean-Marc Valin <[email protected]> Date: Wed Nov 15 04:08:50 2023 -0500 Using sparse GRUs in DRED decoder Saves ~270 kB of weights in the decoder commit 58923f61c26ac0f5d8284d427344466e3bc2c674 Author: Jean-Marc Valin <[email protected]> Date: Sat Nov 11 03:22:34 2023 -0500 Fix non-AVX builds commit 77594bf158bae48c8267f1f548209caa118ae7d5 Author: Jean-Marc Valin <[email protected]> Date: Wed Nov 8 17:32:43 2023 -0500 Dumping RDOVAE stats from XML commit 222662dac8bfbc2d764142d178b91f9d928f56cc Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 7 17:46:38 2023 -0500 DRED: quantize scale and dead zone to 8 bits commit 4e104555e98c8227464f02ee388d983d387612b6 Author: Jan Buethe <[email protected]> Date: Tue Nov 7 15:12:12 2023 +0100 added weight export script for LACE/NoLACE commit 8af5c6b4a13cb66e0f3dcd465c246d2d2e4128c7 Author: Jan Buethe <[email protected]> Date: Tue Nov 7 11:54:22 2023 +0100 added transposed 1d convolutions to wexchange commit b6095cf22d501cb1950685e46b334b0a2ca7e78b Author: Jean-Marc Valin <[email protected]> Date: Tue Nov 7 02:52:40 2023 -0500 DRED code cleanup Removing some indirections commit 0ab0640d4ad41d765ab2b9916f7146c67fe56a3c Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 6 17:49:18 2023 -0500 Split stats in two and remove useless dimensions commit 2386a60ec644fadc437155cd6e5f6d4c561940d4 Author: Jan Buethe <[email protected]> Date: Mon Nov 6 17:50:48 2023 +0100 updated moc to match results in ietf118 presentation commit 544b3e576c8edd1785914c988882b62d60652f26 Author: Jean-Marc Valin <[email protected]> Date: Mon Nov 6 03:10:59 2023 -0500 DRED: quantize r and p0 parameters with 8 bits Only code non-degenerate symbols, which makes the encoder faster commit 98b8be09d56d03d220fff3536842c0703bae865c Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 3 17:28:24 2023 -0400 Vectorize DRED quantization commit fa5e960cb1d968955a4158aa908faa7ee3940aed Author: Felicia Lim <[email protected]> Date: Fri Nov 3 14:53:20 2023 -0700 Match silenced overflow checks in the sse4.1 version Update silk/x86/NSQ_del_dec_sse4_1.c to match the remaining silk/NSQ_del_dec.c changes made in https://gitlab.xiph.org/xiph/opus/-/commit/c913dc38 Signed-off-by: Jean-Marc Valin <[email protected]> commit cfeddc49f9136bf231bddd0f976d94670c200c60 Author: Felicia Lim <[email protected]> Date: Fri Oct 20 13:24:54 2023 -0700 Silence some overflow checks Co-authored-by: James Zern <[email protected]> commit 1ada7d4d6f838dc0842fc89159747755c516ce24 Author: Jean-Marc Valin <[email protected]> Date: Fri Nov 3 02:46:38 2023 -0400 Vectorizing sgemv for multiples of 4 with SSE commit 166a6c8e49fe1335feae6ffc450325f7f5f628c6 Author: Jean-Marc Valin <[email protected]> Date: Tue Oct 31 02:14:03 2023 -0400 Fix silly bug in CELT Deep PLC commit 74c67a8df5c588fd733820eb2f5f3ff59de0e4a3 Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 30 17:14:43 2023 -0400 Fix CELT PLC for single packet between losses Avoids switching to CNG unless we just have a "refresh packet" commit da60266f6e11cb8d2d28aafa8ea05e5dadf3e8b6 Author: Jan Buethe <[email protected]> Date: Thu Nov 2 16:52:50 2023 +0100 updated moc method commit feb32828877ea5e8723ea2a446eb20d7b3fba426 Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 30 14:08:07 2023 -0400 Don't try to use models that aren't loaded commit 62b546436fc07035802eb998f61702ee2716db60 Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 30 00:08:53 2023 -0400 Speed up general case for float matrix multiply commit 61fb3b16894c8fff523efb4255247d151ed5bad5 Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 29 21:19:51 2023 -0400 Don't use reserved identifiers for include guards commit d53531d0bd600e9d1d2400bb801cb381245321c4 Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 29 16:33:57 2023 -0400 Update blob loading code commit 0b75501270eef6477bd337987fd24d92ba80112f Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 29 02:38:21 2023 -0400 Use log approximation when possible commit 4259d354df7159e44b580257981635611ed075ab Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 29 02:20:35 2023 -0400 Reusing already-optimized celt_fir() commit b22b11a412977570ef0a8581cb7ebc9edbaf4e39 Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 29 00:12:58 2023 -0400 Silence some warnings Including removing useless code commit ddd5669e79a9e581e8420d2ed397e524da864337 Author: Jean-Marc Valin <[email protected]> Date: Sat Oct 28 23:33:47 2023 -0400 Pitch and fargan model updates Removing one of the 2d conv layers for pitch estimation reduces complexity without noticeable degradation. FARGAN model has more adversarial training. Also, no need for the double precision in the low-pass filter. commit c99054dad9053ff7dc30cf0379d8aeb240b2e171 Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 27 01:29:56 2023 -0400 Fix CELT deep PLC bugs The sinc filter offset was incorrectly handled. Since it perfectly compensates for the analysis offset, nothing has to be done. Also, the preemphasis memory was never initialized. commit ccb244a73272fa77f1ced18ad2794dcd653749f9 Author: Jean-Marc Valin <[email protected]> Date: Tue Oct 24 09:27:31 2023 -0400 cleanup commit bc102f5fab5848013c51ed22d3b7bbaf9a0a6aca Author: Jean-Marc Valin <[email protected]> Date: Tue Oct 24 09:19:51 2023 -0400 Slightly more continuous analysis commit 64236e5201752ccec137abcd051d1fd4de729670 Author: Jean-Marc Valin <[email protected]> Date: Sat Oct 21 02:26:44 2023 -0400 Removing more useless code commit ef8115bd9a9163a65834298b0dcd702872141523 Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 20 22:07:58 2023 -0400 Stop using tansig_table.h (both copies) commit a30c96aa8a6da49f9844f12fcb40cc9ecf67bf8d Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 20 21:31:19 2023 -0400 Cleanup commit 88c58cfaf37d513b6bd1660617e50e610e1ab58d Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 20 17:08:35 2023 -0400 nnet.h no longer needs to #include "vec.h" commit 1032e47d3f3376947280d2c7769c522b6474c6ad Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 20 15:12:42 2023 -0400 more cleanup commit 7f0d456c4b3c1579f0884f2e26c55fea45d7e00a Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 20 15:05:14 2023 -0400 Remove unneeded functions in nnet.c commit 4598fe540955755c91a432090086d2bdfaab7f03 Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 20 12:54:13 2023 -0400 Quantizing pitchdnn and rdovae weights commit 290be25b982380552ced642e51e225c0bbe9985a Author: Jan Buethe <[email protected]> Date: Fri Oct 20 14:24:27 2023 +0200 added 16kHz version of opus_compare in python commit 1accd2472e678d540fa024f05da68088014dafaa Author: Jan Buethe <[email protected]> Date: Fri Oct 20 14:14:31 2023 +0200 finalized quantization option in export_rdovae_weights.py commit 88c8b3078518b649933616fb7c9a78e4d086233a Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 20 03:28:17 2023 -0400 Doing some unrolling on ARM/Neon commit f512c9206beef41367dff3e0c81fffc374b35efc Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 20 01:33:49 2023 -0400 Unroll the 3x3 convolution case Gets us about 2x speedup on x86 commit d720955d617768aea7271076f3993e6263e8b84f Author: Jean-Marc Valin <[email protected]> Date: Thu Oct 19 16:06:52 2023 -0400 Marking RDOVAE layers to quantize commit 60ac1c6c99153a8ee5ba3e6f9f8fdd1bd3f54dc6 Author: Jan Buethe <[email protected]> Date: Thu Oct 19 21:54:39 2023 +0200 prepared quantization implementation for DRED commit 2192e85b91eca441465ce523162076733584b004 Author: Jan Buethe <[email protected]> Date: Thu Oct 19 21:45:45 2023 +0200 restructured osce readme commit 055c6830189acf0d95422d16bf457344b13b819d Author: Jan Buethe <[email protected]> Date: Thu Oct 19 21:34:13 2023 +0200 added LACE/NoLACE checkpoint URL commit 8d43b185b2bb44841cb9b13e6dc1f4f30da0db87 Author: Jean-Marc Valin <[email protected]> Date: Wed Oct 18 17:40:54 2023 -0400 Support OPUS_SET_COMPLEXITY() on decoder side Controls whether deep PLC is enabled commit 000af0340a6483edc76028e7fcd889b1270f5f80 Author: Jean-Marc Valin <[email protected]> Date: Wed Oct 18 13:00:40 2023 -0400 Avoiding work on the PLC update side Shift computation to concealment commit d1309dd2b62973757c00f476d1cd623147f6e0f1 Author: Jean-Marc Valin <[email protected]> Date: Wed Oct 18 02:56:43 2023 -0400 Simplifying the DRED/PLC code commit 8c7c03e568ae6430018959f3f91d1f5745950069 Author: Jean-Marc Valin <[email protected]> Date: Wed Oct 18 01:44:50 2023 -0400 Don't call the libm tanh() commit 0e397a7241a8dd0021acc0677c80c222c5156440 Author: Jean-Marc Valin <[email protected]> Date: Wed Oct 18 00:43:03 2023 -0400 Making the build possible without the models No dependency on the data files if no DNN code enabled commit aca04ce269eb1e91f353504ed69e15ee3b60fde2 Author: Jean-Marc Valin <[email protected]> Date: Tue Oct 17 01:52:32 2023 -0400 Default to int8 matrix multiplies when available commit f82f9d1ebb340f0848b195d663471b35658d5ccd Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 16 23:10:23 2023 -0400 oops commit e51d3da901703b7c004f4538446aafa7997dafbd Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 16 23:01:17 2023 -0400 Fix tests commit 828f2553d678a590b3d6a65ad8fcd7a5a79046c1 Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 16 22:13:19 2023 -0400 Remove references to kiss99 commit e7c9bfbbe2cc8a49df88d5541df3c094f8aab8e1 Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 16 22:01:09 2023 -0400 Finish removing LPCNet And references to nnet_data.h commit ca035ef1d23912ad8858bcc1833a4aad61db7853 Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 16 16:57:21 2023 -0400 Force Deep PLC on when enabling DRED commit 6471f8013d49e086bf260afd573d4b2c7c7ca018 Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 15 03:53:49 2023 -0400 update weight blob code commit da2121abfff159e69fb0579aa46dce3cae8e5e98 Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 15 03:43:42 2023 -0400 Default Deep PLC/DRED to off commit 6ea9312a93baa663a4695ce89d7d0691a3abb2ce Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 15 03:39:40 2023 -0400 Only compile PLC/DRED conditionally commit 9ed3c7c982d58988a891d8b12d79bd234bd0b806 Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 15 02:45:28 2023 -0400 Rename ENABLE_NEURAL_FED to ENABLE_DRED Signed-off-by: Jean-Marc Valin <[email protected]> commit 5c24975c3a1e46439a37c1a8b16c10515c85d1da Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 15 02:37:54 2023 -0400 Rename NEURAL_PLC to ENABLE_DEEP_PLC Signed-off-by: Jean-Marc Valin <[email protected]> commit 98726c4ca61ddfb691e7fc2dff26d9e51e7fffaa Author: Jean-Marc Valin <[email protected]> Date: Sat Oct 14 23:19:28 2023 -0400 Fix PLC in opus_demo when DRED is not present commit cbd3a80552a918e71ced43e7e2af35092a170629 Author: Jean-Marc Valin <[email protected]> Date: Sat Oct 14 21:19:46 2023 -0400 minor tweaks commit 0b7c02caf4548e3bd90c39c13913146358e4de8b Author: Jean-Marc Valin <[email protected]> Date: Sat Oct 14 17:21:30 2023 -0400 Remove LPCNet from the build commit c0f94366230d14e88b6aa8cf5ec05c1d5a0f49ce Author: Jean-Marc Valin <[email protected]> Date: Sat Oct 14 17:17:40 2023 -0400 Remove FWGAN from the build for now commit 60f151b87d4a2a4e14eff2c7208c96f8618e6f22 Author: Jean-Marc Valin <[email protected]> Date: Fri Aug 4 16:17:24 2023 -0400 Use FARGAN instead of LPCNet in DRED/PLC commit 35cb8d7f669c64a331eadf434bb08ff44b81c48f Author: Jean-Marc Valin <[email protected]> Date: Tue Oct 10 02:18:21 2023 -0400 C implementation of FARGAN commit 9e76a7bfb835ebe7cb97cf24da98462b78de0207 Author: Jean-Marc Valin <[email protected]> Date: Tue Oct 10 00:51:57 2023 -0400 update fargan to match version 45 commit d1c5b32add990473df84e42a8db64851b2dd65f6 Author: Jean-Marc Valin <[email protected]> Date: Sat Oct 7 18:52:22 2023 -0400 Fix warning from casting between 1D and 2D arrays commit 58f3647a04ff01578e872922f3507f78c4d06b5a Author: Jean-Marc Valin <[email protected]> Date: Sat Oct 7 17:54:17 2023 -0400 Fix misc warnings commit 81624caf9ceb452fa8f909dcd8ad14511136da87 Author: Jean-Marc Valin <[email protected]> Date: Sat Oct 7 17:45:39 2023 -0400 Silencing alignment warnings on x86 intrinsics Those intrinsics don't actually require alignment so we're OK commit 0563d71b255c2ef0cb65aab706ecbd44e0328c8d Author: Jan Buethe <[email protected]> Date: Sat Oct 7 18:52:38 2023 +0200 updated osce readme commit 8f9a7e23c8067a90013f3e56592360132af47e7b Author: Jean-Marc Valin <[email protected]> Date: Fri Oct 6 03:11:57 2023 -0400 New model with wider range of bitrates Using a max lambda of 0.04 commit f0ec990dba011b2862c60a8903954d782cb92d19 Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 2 02:23:41 2023 -0400 Switching to neural pitch estimator Remove old pitch estimator and retrain all models commit da7f4c6c99d1f4e4153f97ee5a6bbd07199507f3 Author: Jean-Marc Valin <[email protected]> Date: Mon Oct 2 01:47:46 2023 -0400 update model commit 27663d364188711e5f662304357cb532e689bfe2 Author: Jean-Marc Valin <[email protected]> Date: Thu Sep 21 12:20:11 2023 -0400 Using a DenseNet for DRED commit 8e8edf71bde743c21960a97815f14dd48c86d6ad Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 1 21:34:58 2023 -0400 Remove unneeded (I think) tanh at the end commit 33adba02c7ac5fe1d1f3bd4027f42b87cddc933c Author: Jean-Marc Valin <[email protected]> Date: Sun Oct 1 03:59:17 2023 -0400 First version of pitch DNN C code Totally untested -- most likely doesn't work commit 966a2d22eb0999e9319d1003b4b55d9fd051d33d Author: Jean-Marc Valin <[email protected]> Date: Sat Sep 30 23:43:51 2023 -0400 Code for 2D convolution Untested commit f3b86f941408b37b0c0236eb5b8b09605b8a713b Author: Jean-Marc Valin <[email protected]> Date: Sat Sep 30 02:48:26 2023 -0400 Fix model saving commit 0459a572f592fb07376c480c1ebbf04c16090211 Author: Jan Buethe <[email protected]> Date: Fri Sep 29 15:34:59 2023 +0200 updated PitchDNN export script commit ce28695844c12f43c31b4ee739749883c8b44b17 Author: Jan Buethe <[email protected]> Date: Fri Sep 29 15:31:45 2023 +0200 refactoring and cleanup commit 49014454907d515e3c8ca8b06add78ad74c417d1 Author: Jan Buethe <[email protected]> Date: Fri Sep 29 14:34:11 2023 +0200 fixed type in error message commit c5c214df1b214375fce964949598f5b4405c655e Author: Jan Buethe <[email protected]> Date: Fri Sep 29 14:25:26 2023 +0200 added rudimentary support for dumping nn.Conv2d layers commit 25c65a0c0b9ce8282cfc713a7c0581664c93ab18 Author: Jean-Marc Valin <[email protected]> Date: Wed Sep 27 19:46:40 2023 -0400 Fix stats indexing for state commit 9a7bb764d40b9bb65131b4fa64d88e6b16a4d844 Author: Jean-Marc Valin <[email protected]> Date: Wed Sep 27 13:01:21 2023 -0400 No features skip needed to align pitch features commit a6b4fe375a22976f5897b189c51e0f42cc842f7b Author: Jean-Marc Valin <[email protected]> Date: Wed Sep 27 13:00:12 2023 -0400 Script to compute the groundtruth data using CREPE commit 217c40d4ac4dec24d2fb47efcd34f5c2ca610f09 Author: Jean-Marc Valin <[email protected]> Date: Wed Sep 27 12:57:08 2023 -0400 dump cleanu…
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