riscv: plat-virt: Let CFG_RISCV_PLIC be build time configurable

RISC-V has several standard interrupt controllers supported by QEMU virtual platform. Thus, we allow CFG_RISCV_PLIC to be overridden at build time while keeping the default value enabled. Signed-off-by: Alvin Chang <[email protected]> Reviewed-by: Yu-Chien Peter Lin <[email protected]> Acked-by: Jerome Forissier <[email protected]>
gagachang · Feb 18, 2025 · 6f351b6 · 6f351b6
1 parent 873f5f6
commit 6f351b6
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/core/arch/riscv/plat-virt/conf.mk b/core/arch/riscv/plat-virt/conf.mk
@@ -26,9 +26,11 @@ CFG_TEE_CORE_NB_CORE ?= 1
 CFG_NUM_THREADS ?= 1
 $(call force,CFG_BOOT_SYNC_CPU,n)
 
+# Interrupt controller
+CFG_RISCV_PLIC ?= y
+
 $(call force,CFG_RISCV_M_MODE,n)
 $(call force,CFG_RISCV_S_MODE,y)
-$(call force,CFG_RISCV_PLIC,y)
 $(call force,CFG_SBI_CONSOLE,n)
 $(call force,CFG_16550_UART,y)
 $(call force,CFG_RISCV_TIME_SOURCE_RDTIME,y)