[LLVM][XTHeadVector] Implement intrinsics for vfadd/vfsub/vfrsub. (ru…

…yisdk#91)

* [LLVM][XTHeadVector] Define intrinsic functions.

* [LLVM][XTHeadVector] Define pseudos and pats.

* [LLVM][XTHeadVector] Add test cases.

* [NFC][XTHeadVector] Update Readme.

README.md

@@ -57,6 +57,8 @@ Any feature not listed below but present in the specification should be consider
     - (Done) `13.2. Vector Single-Width Averaging Add and Subtract`
     - (Done) `13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation`
     - (Done) `13.6. Vector Narrowing Fixed-Point Clip Instructions`
+  - (WIP) `14. Vector Floating-Point Instructions`
+    - (Done) `14.2. Vector Single-Width Floating-Point Add/Subtract Instructions`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -864,4 +864,8 @@ let TargetPrefix = "riscv" in {
   defm th_vnclipu : XVSaturatingBinaryABShiftRoundingMode;
   defm th_vnclip : XVSaturatingBinaryABShiftRoundingMode;
 
+  // 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
+  defm th_vfadd : XVBinaryAAXRoundingMode;
+  defm th_vfsub : XVBinaryAAXRoundingMode;
+  defm th_vfrsub : XVBinaryAAXRoundingMode;
 } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -21,6 +21,20 @@ defvar MxListXTHeadV = [V_M1, V_M2, V_M4, V_M8];
 // Used to iterate over all possible extendable LMULs in RVV 0.7.1.
 defvar MxListWXTHeadV = [V_M1, V_M2, V_M4];
 
+class FPR_InfoXTHeadV<int sew> {
+  RegisterClass fprclass = !cast<RegisterClass>("FPR" # sew);
+  string FX = "F" # sew;
+  int SEW = sew;
+  list<LMULInfo> MxList = [V_M1, V_M2, V_M4, V_M8];
+  list<LMULInfo> MxListFW = !if(!eq(sew, 64), [], !listremove(MxList, [V_M8]));
+}
+
+def SCALAR_F16XTHeadV : FPR_InfoXTHeadV<16>;
+def SCALAR_F32XTHeadV : FPR_InfoXTHeadV<32>;
+def SCALAR_F64XTHeadV : FPR_InfoXTHeadV<64>;
+
+defvar FPListXTHeadV = [SCALAR_F16XTHeadV, SCALAR_F32XTHeadV, SCALAR_F64XTHeadV];
+
 // Redefine `AllIntegerVectors` from RISCVInstrInfoVPseudos.td to remove fractionally-grouped register groups
 // like MF2, MF4, MF8, which are not supported by the 'V' extension 0.7.1.
 defset list<VTypeInfo> AllXVectors = {
@@ -1352,11 +1366,11 @@ multiclass XVPatUSLoadStoreWholeVRSDNode<ValueType type,
 }
 
 // Explicitly define the expected instruction selection result for each vector type
-foreach vti = [XVI8M1, XVI16M1, XVI32M1, XVI64M1] in
+foreach vti = [XVI8M1, XVI16M1, XVI32M1, XVI64M1, XVF16M1, XVF32M1, XVF64M1] in
   let Predicates = GetXVTypePredicates<vti>.Predicates in
   defm : XVPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
                                        vti.RegClass>;
-foreach vti = GroupIntegerXVectors in
+foreach vti = !listconcat(GroupIntegerXVectors, GroupFloatXVectors) in
   let Predicates = GetXVTypePredicates<vti>.Predicates in
   defm : XVPatUSLoadStoreWholeVRSDNode<vti.Vector, vti.Log2SEW, vti.LMul,
                                        vti.RegClass>;
@@ -1815,6 +1829,18 @@ multiclass XVPseudoBinaryV_WI_RM<LMULInfo m> {
                                         "@earlyclobber $rd", "")>;
 }
 
+multiclass XVPseudoBinaryFV_VV_RM<LMULInfo m, string Constraint = "", int sew = 0> {
+  defm _VV : XVPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,
+                                       Constraint, sew,
+                                       UsesVXRM=0>;
+}
+
+multiclass XVPseudoBinaryV_VF_RM<LMULInfo m, FPR_InfoXTHeadV f, string Constraint = "", int sew = 0> {
+  defm _V # f.FX : XVPseudoBinaryRoundingMode<m.vrclass, m.vrclass,
+                                              f.fprclass, m, Constraint, sew,
+                                              UsesVXRM=0>;
+}
+
 multiclass XVPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxListXTHeadV in {
     defvar mx = m.MX;
@@ -2219,6 +2245,42 @@ multiclass XVPseudoVNCLP_WV_WX_WI_RM {
   }
 }
 
+multiclass XVPseudoVALU_VV_VF_RM {
+  foreach m = MxListXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVFALUV_MX = !cast<SchedWrite>("WriteVFALUV_" # mx);
+    defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
+
+    defm "" : XVPseudoBinaryFV_VV_RM<m>,
+              Sched<[WriteVFALUV_MX, ReadVFALUV_MX, ReadVFALUV_MX, ReadVMask]>;
+  }
+
+  foreach f = FPListXTHeadV in {
+    foreach m = f.MxList in {
+      defvar mx = m.MX;
+      defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
+      defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
+      defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
+      defm "" : XVPseudoBinaryV_VF_RM<m, f>,
+                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+    }
+  }
+}
+
+multiclass XVPseudoVALU_VF_RM {
+  foreach f = FPListXTHeadV in {
+    foreach m = f.MxList in {
+      defvar mx = m.MX;
+      defvar WriteVFALUF_MX = !cast<SchedWrite>("WriteVFALUF_" # mx);
+      defvar ReadVFALUV_MX = !cast<SchedRead>("ReadVFALUV_" # mx);
+      defvar ReadVFALUF_MX = !cast<SchedRead>("ReadVFALUF_" # mx);
+
+      defm "" : XVPseudoBinaryV_VF_RM<m, f>,
+                Sched<[WriteVFALUF_MX, ReadVFALUV_MX, ReadVFALUF_MX, ReadVMask]>;
+    }
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns for the XTHeadVector extension.
 //===----------------------------------------------------------------------===//
@@ -3389,4 +3451,21 @@ let Predicates = [HasVendorXTHeadV] in {
                                    AllWidenableIntXVectors>;
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXTHeadV], mayRaiseFPException = true, hasPostISelHook = 1 in {
+  defm PseudoTH_VFADD  : XVPseudoVALU_VV_VF_RM;
+  defm PseudoTH_VFSUB  : XVPseudoVALU_VV_VF_RM;
+  defm PseudoTH_VFRSUB : XVPseudoVALU_VF_RM;
+}
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryV_VV_VX_RM<"int_riscv_th_vfadd", "PseudoTH_VFADD",
+                               AllFloatXVectors>;
+  defm : XVPatBinaryV_VV_VX_RM<"int_riscv_th_vfsub", "PseudoTH_VFSUB",
+                               AllFloatXVectors>;
+  defm : XVPatBinaryV_VX_RM<"int_riscv_th_vfrsub", "PseudoTH_VFRSUB", AllFloatXVectors>;
+}
+
 include "RISCVInstrInfoXTHeadVVLPatterns.td"