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[SYCL][E2E] Cleanup compilation redundancies for FPGA archive tests #12850

[SYCL][E2E] Cleanup compilation redundancies for FPGA archive tests

[SYCL][E2E] Cleanup compilation redundancies for FPGA archive tests #12850

Triggered via pull request January 10, 2025 00:34
Status Success
Total duration 1h 9m 8s
Artifacts 1

sycl-windows-precommit.yml

on: pull_request
detect_changes  /  Decide which tests could be affected by the changes
4s
detect_changes / Decide which tests could be affected by the changes
e2e  /  Intel GEN12 Graphics with Level Zero
50m 37s
e2e / Intel GEN12 Graphics with Level Zero
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sycl_windows_default
580 MB