1. Hardware Details

Introduction

The Compaq S3 Virge GX uses the S3 Virge GX 86C385 chipset. This chipset does not have any datasheet available, but its earlier sibling, the S3 Virge 86C375, has its full datasheet available online.

The Virge supports up to 4MB of EDO RAM, instead of the SGRAM used on this Virge GX card. Therefore the actual signals were different and this had me confused for some time.

Signals & Pinout

The Virge GX, exactly like the Virge, uses a 10-bit address bus and a 64bit-wide data bus. Two 100MHz 128K x 32-bit x 2 banks SGRAM chips were used to consist one half of the supported memory space.

The Virge uses RAS0 and RAS1 lines to select different halves of the supported VRAM space (0-2MB v.s. 2-4MB). However with the GX, this was changed. The GX uses pin 177 and 196 for the respective memory spaces and connect to the CS# line on the actual ram chips. Pin 177 and 196 were both marked N/C on the datasheet of the Virge, so you might be able to imagine the mystery and confusion.

The pin headers mirror the signals going to the onboard RAM banks, except for the CS signal. I still had to painstakingly map it out in order to be able to move forward.

During the mapping process, I noticed the BIOS chip also sits on the data bus, with the extra CE# and OE# pins to control its behavior. This made it possible to add a BIOS socket on the add-on board with only two extra lines that need to be bodged to the bottom connector.

Pinout

Pin number goes from left to right, and top to bottom.

I used a two-part format to remind myself how signals went from the chipset to the RAM chips: - e.g. PD44-DQ12

Top Connector

Pin	Definition	Pin	Definition	Pin	Definition	Pin	Definition
1	PD44-DQ12	21	GND	41	PD43-DQ11	61	PD42-DQ10
2	GND	22	PD35-DQ03	42	PD36-DQ04	62	GND
3	PD34-DQ02	23	GND	43	PD37-DQ05	63	PD41-DQ09
4	PD33-DQ01	24	PD45-DQ13	44	GND	64	PD38-DQ06
5	GND	25	PD46-DQ14	45	PD40-DQ08	65	GND
6	PD32-DQ00	26	NC/NPTH	46	GND	66	PD39-DQ07
7	PD47-DQ15	27	GND	47	PD63-DQ31	67	PD62-DQ30
8	GND	28	PD48-DQ16	48	PD61-DQ29	68	GND
9	PD49-DQ17	29	GND	49	PD60-DQ28	69	PD59-DQ27
10	PD50-DQ18	30	PD51-DQ19	50	GND	70	PD58-DQ26
11	GND	31	PD52-DQ20	51	PD57-DQ25	71	GND
12	PD53-DQ21	32	PD54-DQ22	52	GND	72	PD56-DQ24
13	OE0-CAS	33	GND	53	PD55-DQ23	73	WE
14	GND	34	8K3V3-HCKE	54	NC	74	GND
15	PD07-DQ07	35	GND	55	PD15-DQ15	75	PD14-DQ14
16	PD06-DQ06	36	PD05-DQ05	56	GND	76	PD13-DQ13
17	GND	37	PD04-DQ04	57	PD12-DQ12	77	GND
18	PD03-DQ03	38	PD02-DQ02	58	GND	78	PD11-DQ11
19	PD01-DQ01	39	GND	59	PD10-DQ10	79	PD09-DQ09
20	GND	40	PD00-DQ00	60	PD08-DQ08	80	GND

Bottom Connector

In order to connect the optional BIOS, I used pin 39 and 80, which were NC, as the CE# and OE# signals.

Pin	Definition	Pin	Definition	Pin	Definition	Pin	Definition
1	GND	21	CAS7-HDQM3	41	CAS6-HDQM2	61	GND
2	CAS4-HDQM0	22	GND	42	CAS3-LDQM3	62	CAS5-HDQM1
3	CAS2-LDQM2	23	3V3-H	43	GND	63	CAS1-LDQM1
4	GND	24	3V3-H	44	RAS0-HCLK	64	GND
5	179-DSF	25	CAS0-LDQM0	45	GND	65	3V3-H
6	181-BA	26	GND	46	NC/NPTH	66	RAS0-LCLK
7	GND	27	196-CS	47	OE1-RAS	67	GND
8	MA8-A8	28	GND	48	MA6-A6	68	3V3-H
9	MA5-A5	29	MA7-A7	49	GND	69	MA4-A4
10	GND	30	MA3-A3	50	MA1-A1	70	GND
11	MA2-A2	31	3V3-H	51	GND	71	MA0-A0
12	PD24-DQ24	32	GND	52	PD23-DQ23	72	3V3-L
13	GND	33	PD25-DQ25	53	PD22-DQ22	73	GND
14	PD26-DQ26	34	GND	54	PD20-DQ20	74	PD21-DQ21
15	3V3-L	35	PD27-DQ27	55	GND	75	3V3-L
16	GND	36	PD28-DQ28	56	PD19-DQ19	76	GND
17	PD30-DQ30	37	PD29-DQ29	57	GND	77	PD18-DQ18
18	PD31-DQ31	38	GND	58	PD16-DQ16	78	PD17-DQ17
19	GND	39	NC (BIOS CE#)	59	3V3-L	79	GND
20	3V3-L	40	GND	60	8K3V3-LCKE	80	NC (BIOS OE#)

BIOS Chip

The BIOS chip is an AMTEL AT27LV512A OTP EPROM. This chip has a strangely shifted pinout compared to the most commonly found flash/EEPROM chips available nowadays.

AT27LV512A on the outside, SST39VF010 on the inside

The address and data pins of the BIOS chip are all connected to the PD lines on the chipset, and controlled by extra CE# and OE# signals.

• A0 to A15: PD0 to PD15
• D0 to D7: PD16 to PD23
• CE#
• OE#
• WE# (pulled to Vcc)