Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Fixture additions #312

Open
wants to merge 80 commits into
base: master
Choose a base branch
from
Open

Fixture additions #312

wants to merge 80 commits into from

Conversation

leonardt
Copy link
Owner

See original PR: #307

Opening a new one using an internal branch for CI.

@standanley
Quick fix adding the minimum amount of code to get the functionality …
3dfc51d 
…I need
@standanley
Fixed style in new test
8c92eb0
@standanley
Fix indexing into one bit of a spice bus
e744e1e
@standanley
Merge pull request #1 from standanley/spice_bus_indexing
e72dda3 
Fix indexing into one bit of a spice bus
@standanley
Merge remote-tracking branch 'upstream/master'
deaea62
@standanley
Wrote background poke Thread class
311d6d3
@standanley
Finished writing background poke interleaving but have not even run i…
26a0eb4 
…t yet
@standanley
I think it is working for spice targets.
0368670
@standanley
Working on tests for background pokes
95ddd0b
@standanley
Changed location of unit conversion in spice_target
794d7a3
@standanley
Added Print action and nothing more
2ff5d92
@standanley
Added read to VerilogTarget but no implementation
5276903
@standanley
Reading now works for systemverilog targets
7c94e67
@standanley
Reads work for spice too, based on minimal testing
78abb7c
@standanley
Edge finder is now working. Need to clean up prints
64bd264
@standanley
Allow indexing into spice buses
6198fa2
@standanley
Phase measurement now working in spice
e5f9ecb
@standanley
Deleted some debugging prints
6a61712
@standanley
Fixed bug in phase measurement and added test
4272bb4
@standanley
Merged spice_timing into read_action but some of the read_action test…
8a23678 
…s are broken
@standanley
Changed background poke so it would not break spice reads. Still an i…
35faadf 
…ssue with verilog reads
@standanley
Fixed default clock step
893c859
@standanley
Fixed bug with clocks in background_poke
7aa57ff
@standanley
Changed pwc to pwl conversion to allow two points within rt of each o…
bfeba86 
…ther
@standanley
Changed spice_target to print stderr of simulation command
2dc8063
@standanley
Marked read action as not implemented in verilator_target
ae39e7a
@standanley
Bugfix and labeling of error output.
a6542d0
@standanley
New read styles, decreased default step size in spice transient sim
4939b87
@standanley
fixed issue with block reads beyond the end of simulation time
096a74f
@standanley
Got rid of some references to old style read using save_for_later. St…
657e003 
…ill need to fix tests, but will wait until after merge
standanley and others added 29 commits April 2, 2020 12:20
@standanley
Merge branch 'add_flatten' into combine_branches
686b158
@standanley
Delete traces of old Read action (replaced by GetValue)
7c5fe10
@standanley
Fix floating point equality comparison
a255b2c
@standanley
Fixes for arrays of analog and outputs that are arrays
b921caa
@standanley
Slight update to verilog_target for domain_read
f990113
@standanley
Working on merge
83b3c73
@standanley
Fix mistake in merge of result_parse
41c85ec
@standanley
Add new type of background poke called future. Doesn't work yet so I'…
0c1d6d2 
…m about to make minor changes to background poke class
@standanley
Updates before dragonphy integration
8639507
@standanley
Fixed minor merge conflicts in system_verilog_target
773fd1e
@standanley
Very minor updates to tests
ba86b16
@standanley
Very minor organization changes
30710cd
@standanley
Update background_poke and mlingua_interface decorators to handle arb…
a4b0233 
…itrary args to run()
@standanley
Special case in background_poke for when the port is a Var action. Ri…
6dfd620 
…ght now it will likely crash if a var is background-poked and work incorrectly if a poke to a var is used to override an existing background poke.
@standanley
Working on get_value_domain. Seems to work for SystemVerilog
03be393
@standanley
Merge branch 'master' into fixture_additions_merge
63e3bc9
@standanley
Fix timescale read issue spice result parsing.
8830a6e
@standanley
Various style improvements before pull request
92af1a0
@standanley
Clean up background poke tests
1cb8911
@standanley
Cleanup and bugfixes regarding get value domain for spice circuits
6bd9119
@standanley
Remove mlingua stuff. Hopefully it will be added in the future
df7f4b5
@standanley
Style cleanup
898161e
@standanley
More style improvements. Also undid 'style improvement' that broke a …
d137e55 
…test
@standanley
First pass at adding current input in SpiceTarget. Seems to work; cur…
10dbb2e 
…rent output is next
@standanley
Added current outputs
312f706
@standanley
Fix current changes to work with buses. Also fix test_spice_bus to ma…
51b8702 
…nually add delays between poke and expect.
@standanley
Minor changes to fix small bugs
00c2469
@standanley
Rewrite buggy background_poke clock method. I think the new approach …
157932c 
…is much better.
@leonardt
Merge pull request #307 from standanley/fixture_additions
4441d2d 
Fixture additions
@leonardt leonardt mentioned this pull request Aug 13, 2021
Merged
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@leonardt @standanley