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[SelectionDAG] WidenVecOp_INSERT_SUBVECTOR - Replace INSERT_SUBVECTOR with series of INSERT_VECTOR_ELT #124420

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merged 6 commits into from
Jan 28, 2025

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abhishek-kaushik22
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If the operands to INSERT_SUBVECTOR can't be widened legally, just replace the INSERT_SUBVECTOR with a series of INSERT_VECTOR_ELT.

Closes #124255 (and possibly #102016)

…OR_ELT`

If the operands to `INSERT_SUBVECTOR` can't be widened legally, just replace the `INSERT_SUBVECTOR` with a series of `INSERT_VECTOR_ELT`.

Closes llvm#124255 (and possibly llvm#102016)
@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Jan 25, 2025
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llvmbot commented Jan 25, 2025

@llvm/pr-subscribers-backend-x86

@llvm/pr-subscribers-llvm-selectiondag

Author: None (abhishek-kaushik22)

Changes

If the operands to INSERT_SUBVECTOR can't be widened legally, just replace the INSERT_SUBVECTOR with a series of INSERT_VECTOR_ELT.

Closes #124255 (and possibly #102016)


Full diff: https://github.com/llvm/llvm-project/pull/124420.diff

1 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (+22-4)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index f39d9ca15496a9..81cf1afe746e88 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -7040,8 +7040,11 @@ SDValue DAGTypeLegalizer::WidenVecOp_INSERT_SUBVECTOR(SDNode *N) {
   SDValue SubVec = N->getOperand(1);
   SDValue InVec = N->getOperand(0);
 
-  if (getTypeAction(SubVec.getValueType()) == TargetLowering::TypeWidenVector)
-    SubVec = GetWidenedVector(SubVec);
+  SDValue OrigSubVec;
+  if (getTypeAction(SubVec.getValueType()) == TargetLowering::TypeWidenVector) {
+    OrigSubVec = std::move(SubVec);
+    SubVec = GetWidenedVector(OrigSubVec);
+  }
 
   EVT SubVT = SubVec.getValueType();
 
@@ -7070,8 +7073,23 @@ SDValue DAGTypeLegalizer::WidenVecOp_INSERT_SUBVECTOR(SDNode *N) {
     return DAG.getNode(ISD::INSERT_SUBVECTOR, SDLoc(N), VT, InVec, SubVec,
                        N->getOperand(2));
 
-  report_fatal_error("Don't know how to widen the operands for "
-                     "INSERT_SUBVECTOR");
+  // If the operands can't be widened legally, just replace the INSERT_SUBVECTOR
+  // with a series of INSERT_VECTOR_ELT
+  EVT OrigVT = OrigSubVec.getValueType();
+  unsigned Idx = N->getConstantOperandVal(2);
+
+  SDValue InsertVecElt;
+  SDLoc DL(N);
+  for (unsigned I = 0; I < OrigVT.getVectorNumElements(); ++I) {
+    SDValue Extract =
+        DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT.getScalarType(), SubVec,
+                    DAG.getIntPtrConstant(I, DL, /*isTarget*/ true));
+    InsertVecElt = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT,
+                               I != 0 ? InsertVecElt : InVec, Extract,
+                               DAG.getIntPtrConstant(I + Idx, DL, true));
+  }
+
+  return InsertVecElt;
 }
 
 SDValue DAGTypeLegalizer::WidenVecOp_EXTRACT_SUBVECTOR(SDNode *N) {

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RKSimon commented Jan 25, 2025

Test cases?

Comment on lines 31 to 47
define <8 x i32> @insert_i32_v2_in_v8_at_0(<8 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: insert_i32_v2_in_v8_at_0:
; CHECK: # %bb.0:
; CHECK-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
; CHECK-NEXT: retq
%result = tail call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> %a, <2 x i32> %b, i64 0)
ret <8 x i32> %result
}

define <8 x i32> @insert_i32_v2_in_v8_at_6(<8 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: insert_i32_v2_in_v8_at_6:
; CHECK: # %bb.0:
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; CHECK-NEXT: retq
%result = tail call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> %a, <2 x i32> %b, i64 6)
ret <8 x i32> %result
}
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Do we need to test <8 x i32>? Or should add -mattr=+avx to enable 256-bit vector?

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https://godbolt.org/z/zE86YKMY1

I still see a crash with -mattr=+avx, the problem is not the <8 x i32> vector, it's the <2 x i32> which when widened becomes <4 x i32>.

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Maybe they are not needed?

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Please let me know if you think that's the case, I'm okay to remove them.

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Ideally we should fix the AVX case as well - it'd be OK to keep the tests for now and add -mattr=+avx test coverage along with the fix in a future PR

@RKSimon RKSimon changed the title [SelectionDAG] Replace INSERT_SUBVECTOR with series of INSERT_VECTOR_ELT [SelectionDAG] WidenVecOp_INSERT_SUBVECTOR - Replace INSERT_SUBVECTOR with series of INSERT_VECTOR_ELT Jan 27, 2025
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Outdated Show resolved Hide resolved
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Outdated Show resolved Hide resolved
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Outdated Show resolved Hide resolved
llvm/test/CodeGen/X86/pr124255.ll Outdated Show resolved Hide resolved
Comment on lines 31 to 47
define <8 x i32> @insert_i32_v2_in_v8_at_0(<8 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: insert_i32_v2_in_v8_at_0:
; CHECK: # %bb.0:
; CHECK-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
; CHECK-NEXT: retq
%result = tail call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> %a, <2 x i32> %b, i64 0)
ret <8 x i32> %result
}

define <8 x i32> @insert_i32_v2_in_v8_at_6(<8 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: insert_i32_v2_in_v8_at_6:
; CHECK: # %bb.0:
; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm2[0]
; CHECK-NEXT: retq
%result = tail call <8 x i32> @llvm.vector.insert.v8i32.v2i32(<8 x i32> %a, <2 x i32> %b, i64 6)
ret <8 x i32> %result
}
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Ideally we should fix the AVX case as well - it'd be OK to keep the tests for now and add -mattr=+avx test coverage along with the fix in a future PR

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LGTM

@abhishek-kaushik22 abhishek-kaushik22 merged commit 015aed1 into llvm:main Jan 28, 2025
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LLVM ERROR: Don't know how to widen the operands for INSERT_SUBVECTOR
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