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@guilhermerc
guilhermerc committed Apr 20, 2023
2 parents bdbc760 + 6ede570 commit 6333cac
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Showing 39 changed files with 21,494 additions and 6,252 deletions.
2 changes: 1 addition & 1 deletion hdl/ip_cores/general-cores
Submodule general-cores updated 96 files
+48 −0 CHANGELOG.rst
+7 −2 README.md
+292 −248 modules/axi/axi4_pkg.vhd
+3 −1 modules/common/Manifest.py
+3 −4 modules/common/gc_arbitrated_mux.vhd
+0 −1 modules/common/gc_big_adder.vhd
+267 −460 modules/common/gc_ds182x_readout/gc_ds182x_readout.vhd
+0 −1 modules/common/gc_dyn_extend_pulse.vhd
+117 −0 modules/common/gc_edge_detect.vhd
+369 −302 modules/common/gc_enc_8b10b.vhd
+2 −3 modules/common/gc_extend_pulse.vhd
+2 −2 modules/common/gc_fsm_watchdog.vhd
+1 −2 modules/common/gc_moving_average.vhd
+18 −13 modules/common/gc_negedge.vhd
+18 −13 modules/common/gc_posedge.vhd
+23 −18 modules/common/gc_pulse_synchronizer2.vhd
+206 −0 modules/common/gc_simple_spi_master.vhd
+6 −5 modules/common/gc_sync.vhd
+0 −70 modules/common/gc_sync_edge.vhd
+16 −7 modules/common/gc_sync_ffs.vhd
+6 −4 modules/common/gc_sync_word_wr.vhd
+4 −4 modules/common/gc_word_packer.vhd
+25 −18 modules/common/gencores_pkg.vhd
+14 −10 modules/genrams/Manifest.py
+1 −0 modules/genrams/altera/generic_dpram.vhd
+4 −0 modules/genrams/cheby/Manifest.py
+86 −0 modules/genrams/cheby/cheby_dpssram.vhd
+58 −0 modules/genrams/cheby/cheby_pkg.vhd
+1 −0 modules/genrams/common/Manifest.py
+201 −0 modules/genrams/common/inferred_async_fwft_fifo.vhd
+43 −2 modules/genrams/common/inferred_sync_fifo.vhd
+12 −4 modules/genrams/generic/generic_sync_fifo.vhd
+54 −5 modules/genrams/genram_pkg.vhd
+2 −4 modules/genrams/xilinx/series7/generic_async_fifo.vhd
+2 −4 modules/genrams/xilinx/series7/generic_sync_fifo.vhd
+3 −1 modules/wishbone/Manifest.py
+125 −125 modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+185 −191 modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+9 −1 modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.cheby
+114 −110 modules/wishbone/wb_ds182x_readout/wb_ds182x_regs.vhd
+10 −3 modules/wishbone/wb_ds182x_readout/xwb_ds182x_readout.vhd
+8 −0 modules/wishbone/wb_fine_pulse_gen/Manifest.py
+248 −0 modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7.vhd
+107 −0 modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintex7_shared.vhd
+435 −0 modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale.vhd
+271 −0 modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_kintexultrascale_shared.vhd
+860 −0 modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.vhd
+671 −0 modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wb.wb
+238 −0 modules/wishbone/wb_fine_pulse_gen/fine_pulse_gen_wbgen2_pkg.vhd
+531 −0 modules/wishbone/wb_fine_pulse_gen/xwb_fine_pulse_gen.vhd
+1 −0 modules/wishbone/wb_indirect/Manifest.py
+26 −0 modules/wishbone/wb_indirect/wb_indirect_regs.cheby
+147 −0 modules/wishbone/wb_indirect/wb_indirect_regs.vhd
+153 −0 modules/wishbone/wb_indirect/xwb_indirect.vhd
+0 −44 modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
+1 −1 modules/wishbone/wb_uart/build_wb.sh
+105 −49 modules/wishbone/wb_uart/simple_uart_pkg.vhd
+350 −261 modules/wishbone/wb_uart/simple_uart_wb.vhd
+100 −1 modules/wishbone/wb_uart/simple_uart_wb.wb
+186 −56 modules/wishbone/wb_uart/wb_simple_uart.vhd
+11 −2 modules/wishbone/wb_uart/xwb_simple_uart.vhd
+3 −0 modules/wishbone/wb_xc7_fw_update/Manifest.py
+37 −0 modules/wishbone/wb_xc7_fw_update/wb_xc7_fw_update_regs.cheby
+126 −0 modules/wishbone/wb_xc7_fw_update/wb_xc7_fw_update_regs.vhd
+110 −0 modules/wishbone/wb_xc7_fw_update/xwb_xc7_fw_update.vhd
+11 −5 modules/wishbone/wishbone_pkg.vhd
+7 −3 sim/if_wb_master.svh
+14 −8 sim/if_wishbone_accessor.svh
+4 −4 sim/simdrv_defs.svh
+1 −0 sim/vhdl/Manifest.py
+165 −0 sim/vhdl/sim_wishbone.vhd
+85 −0 sim/vhdl/sim_wishbone16.vhd
+24 −26 software/htvic/drivers/htvic.c
+4 −0 software/i2c-ocores/drivers/i2c/busses/i2c-ocores.c
+8 −1 software/spi-ocores/drivers/spi/spi-ocores.c
+17 −0 testbench/common/gc_ds182x_readout/Manifest.py
+210 −0 testbench/common/gc_ds182x_readout/gc_ds182x_readout_tb.vhd
+0 −0 testbench/wishbone/gc_sync_word_wr/run.do
+0 −0 testbench/wishbone/gc_sync_word_wr/tb_gc_sync_word_wr.vhd
+0 −0 testbench/wishbone/gc_sync_word_wr/wave.do
+160 −0 testbench/wishbone/include/wb_fine_pulse_gen_regs.vh
+15 −0 testbench/wishbone/wb_fine_pulse_gen/Manifest.py
+310 −0 testbench/wishbone/wb_fine_pulse_gen/main.sv
+13 −0 testbench/wishbone/wb_fine_pulse_gen/run.do
+9 −0 testbench/wishbone/wb_indirect/Manifest.py
+47 −0 testbench/wishbone/wb_indirect/tb_indirect.gtkw
+106 −0 testbench/wishbone/wb_indirect/tb_wb_indirect.vhd
+8 −0 testbench/wishbone/wb_spi/Manifest.py
+8 −0 testbench/wishbone/wb_spi/run.do
+74 −0 testbench/wishbone/wb_spi/tb_spi.vhd
+14 −0 testbench/wishbone/wb_uart/Manifest.py
+321 −0 testbench/wishbone/wb_uart/main.sv
+12 −0 testbench/wishbone/wb_uart/run.do
+130 −0 testbench/wishbone/wb_uart/wave.do
+18 −1 tools/gen_buildinfo.py
+41 −0 tools/gen_sourceid.py
1 change: 1 addition & 0 deletions hdl/modules/Manifest.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,5 +3,6 @@
modules = { "local": [
"fofb_ctrl_wrapper",
"fofb_processing",
"fofb_sys_id"
]
}
57 changes: 53 additions & 4 deletions hdl/modules/fofb_ctrl_pkg.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@ library work;
use work.fofb_cc_pkg.all;
use work.wishbone_pkg.all;
use work.dot_prod_pkg.all;
use work.fofb_sys_id_pkg.all;

package fofb_ctrl_pkg is

Expand Down Expand Up @@ -580,6 +581,12 @@ package fofb_ctrl_pkg is
-- Set-point valid array (for each channel)
sp_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0);

-- Decimated setpoint (for each channel)
sp_decim_arr_o : out t_fofb_processing_sp_decim_arr(g_CHANNELS-1 downto 0);

-- Decimated setpoint valid (for each channel)
sp_decim_valid_arr_o : out std_logic_vector(g_CHANNELS-1 downto 0);

dcc_p2p_en_o : out std_logic;

---------------------------------------------------------------------------
Expand All @@ -590,6 +597,31 @@ package fofb_ctrl_pkg is
);
end component;

component xwb_fofb_sys_id is
generic (
g_BPM_POS_INDEX_WIDTH : natural := 9;
g_BPM_POS_WIDTH : natural := c_BPM_POS_WIDTH;
g_MAX_NUM_BPM_POS : natural := c_MAX_NUM_P2P_BPM_POS/2;
g_INTERFACE_MODE : t_wishbone_interface_mode := CLASSIC;
g_ADDRESS_GRANULARITY : t_wishbone_address_granularity := WORD;
g_WITH_EXTRA_WB_REG : boolean := false
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
bpm_pos_i : in signed(c_SP_POS_RAM_DATA_WIDTH-1 downto 0);
bpm_pos_index_i : in unsigned(c_SP_COEFF_RAM_ADDR_WIDTH-1 downto 0);
bpm_pos_valid_i : in std_logic;
bpm_pos_flat_clear_i : in std_logic;
bpm_pos_flat_x_o : out t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0);
bpm_pos_flat_x_rcvd_o : out std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0);
bpm_pos_flat_y_o : out t_bpm_pos_arr(g_MAX_NUM_BPM_POS-1 downto 0);
bpm_pos_flat_y_rcvd_o : out std_logic_vector(g_MAX_NUM_BPM_POS-1 downto 0);
wb_slv_i : in t_wishbone_slave_in;
wb_slv_o : out t_wishbone_slave_out
);
end component;

component fofb_processing_dcc_adapter is
generic (
-- DCC packet FIFO depth
Expand Down Expand Up @@ -667,20 +699,37 @@ package fofb_ctrl_pkg is
-- FOFB Processing
constant c_xwb_fofb_processing_regs_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"02",
abi_ver_major => x"03",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000007FFF",
addr_last => x"000000000000FFFF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"49681ca6",
version => x"00000001",
date => x"20220809",
version => x"00000002",
date => x"20230215",
name => "FOFB_PROC_REGS ")));

-- FOFB system identification
constant c_xwb_fofb_sys_id_regs_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"00",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity (0100)
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000FFFF",
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"4b2f4872", -- Last 8 chars of "FOFB_SYS_ID_REGS" md5sum
version => x"00000001",
date => x"20230404",
name => "FOFB_SYS_ID_REGS ")));

end fofb_ctrl_pkg;

package body fofb_ctrl_pkg is
Expand Down
2 changes: 1 addition & 1 deletion hdl/modules/fofb_processing/cheby/build_cheby.sh
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Original file line number Diff line number Diff line change
@@ -1,3 +1,3 @@
#!/bin/bash

cheby -i wb_fofb_processing_regs.cheby --hdl vhdl --gen-wbgen-hdl wb_fofb_processing_regs.vhd --doc html --gen-doc doc/wb_fofb_processing_regs.html --gen-c wb_fofb_processing_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_fofb_processing_regs.vh --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_processing_regs_consts_pkg.vhd
cheby -i wb_fofb_processing_regs.cheby --hdl vhdl --gen-hdl wb_fofb_processing_regs.vhd --doc html --gen-doc doc/wb_fofb_processing_regs.html --gen-c wb_fofb_processing_regs.h --consts-style verilog --gen-consts ../../../sim/regs/wb_fofb_processing_regs.vh --consts-style vhdl-ohwr --gen-consts ../../../sim/regs/wb_fofb_processing_regs_consts_pkg.vhd
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