Fix typo

README.adoc

@@ -34,7 +34,7 @@ To make it easier to download, each HTML page contains embedded CSS and images.
 ** https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol3-EN.pdf[PDF version].
 ** https://github.com/loongson/LoongArch-Documentation/releases/latest/download/LoongArch-Vol3-v1.00-CN.pdf[Original document].
 
-* Loongson 3A5000/3B5000 Registers Technical Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide: This manual introduces the Loongson 3A5000/3B5000 multicore processor architecture and register descriptions.
+* Loongson 3A5000/3B5000 Processor Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide: This manual introduces the Loongson 3A5000/3B5000 multicore processor architecture and register descriptions.
 ** https://loongson.github.io/LoongArch-Documentation/Loongson-3A5000-usermanual-EN.html[HTML version].
 ** https://loongson.github.io/LoongArch-Documentation/Loongson-3A5000-usermanual-EN.pdf[PDF version].
 ** https://github.com/loongson/LoongArch-Documentation/releases/latest/download/Loongson-3A5000-usermanual-v1.02-CN.pdf[Original document].

Rakefile

@@ -6,8 +6,9 @@ namespace :book do
 
     desc 'generate contributors list'
     task :generate do |t|
+        ENV["LC_ALL"] = "C"
         puts 'Generating contributors list...'
-        `git shortlog --summary --email HEAD | grep -v -E "users\.noreply\.github\.com" | cut -f 2- | LC_ALL=C sort --ignore-case > contributors.txt`
+        `git shortlog --summary --email HEAD | grep -v -E "users\.noreply\.github\.com" | cut -f 2- | sort --ignore-case > contributors.txt`
         puts ' -- contributors list generation done!'
     end
 

docs/Loongson-3A5000-usermanual-EN.adoc

@@ -1,4 +1,4 @@
-= Loongson 3A5000/3B5000 Registers Technical Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide
+= Loongson 3A5000/3B5000 Processor Reference Manual - Multicore Processor Architecture, Register Descriptions and System Software Programming Guide
 Loongson Technology Corporation Limited
 v1.03
 :title-separator: -

docs/Loongson-3A5000-usermanual-EN/chip-clock-division-and-enable-control/processor-core-frequency-division-and-enable-control/accessing-by-configuration-register-instructions.adoc

@@ -1,7 +1,7 @@
 [[accessing-by-configuration-register-instructions-1]]
 ==== Accessing by Configuration Register Instructions
 
-In addition to the traditional per-address access mode, the 3A5000 also supports access to private frequency division configuration registers using the configuration register instruction.
+In addition to the legacy per-address access mode, the 3A5000 also supports access to private frequency division configuration registers using the configuration register instruction.
 
 Note that the private frequency division configuration register control is mutually exclusive with the original processor core software frequency division setup register control, and only one of the two can be used.
 The choice is made by using the corresponding bit on the other function configuration register.

docs/Loongson-3A5000-usermanual-EN/chip-configuration-register/chip-characteristics-register.adoc

@@ -78,7 +78,7 @@ d|Reset Value
 |Flat Mode
 |R
 |1'b0
-|Traditional compatibility mode
+|Legacy compatibility mode
 
 |11
 |Guest Mode

docs/Loongson-3A5000-usermanual-EN/hypertransport-controller/hypertransport-interrupt-support/local-interrupts-handling.adoc

@@ -1,7 +1,7 @@
 [[local-interrupts-handling]]
 ==== Local Interrupts Handling
 
-In the traditional interrupt handling model, all interrupts are stored by the interrupt vector inside the HT controller and then distributed through the interrupt line of the HT controller connected to the interrupt router on the chip.
+In the legacy interrupt handling model, all interrupts are stored by the interrupt vector inside the HT controller and then distributed through the interrupt line of the HT controller connected to the interrupt router on the chip.
 In this case, HT interrupts are only available to CPU cores through a limited number of connections, and cannot be distributed across chips, so the usage scenario is rather limited.
 
 In this HT interrupt mode, when performing interrupt processing, the interrupt router on the chip is transparent to the software and the core goes directly to the interrupt vector of the HT controller (typically `0x90000efdfb000080`) for lookup and then per-bit processing.

docs/Loongson-3A5000-usermanual-EN/io-interrupts.adoc

@@ -2,9 +2,9 @@
 == I/O Interrupts
 
 The Loongson 3A5000 chip supports two different interrupt methods.
-The first is the traditional interrupt method, which is compatible with processors such as the 3A3000, and the second is the new extended I/O interrupt method, which is used to support the interrupt cross-chip and dynamic distribution functions of the HT controller.
+The first is the legacy interrupt method, which is compatible with processors such as the 3A3000, and the second is the new extended I/O interrupt method, which is used to support the interrupt cross-chip and dynamic distribution functions of the HT controller.
 The following describes each of the two interrupt methods.
 
-include::io-interrupts/traditional-io-interrupts.adoc[]
+include::io-interrupts/legacy-io-interrupts.adoc[]
 
 include::io-interrupts/extended-io-interrupts.adoc[]

docs/Loongson-3A5000-usermanual-EN/io-interrupts/extended-io-interrupts.adoc

@@ -1,7 +1,7 @@
 [[extended-io-interrupts]]
 === Extended I/O Interrupts
 
-In addition to being compatible with the traditional I/O interrupt method, the 3A5000 supports extended I/O interrupts, which are used to distribute 256-bit interrupts on the HT bus directly to each processor core instead of forwarding them through the HT interrupt line, increasing the flexibility of I/O interrupt usage.
+In addition to being compatible with the legacy I/O interrupt method, the 3A5000 supports extended I/O interrupts, which are used to distribute 256-bit interrupts on the HT bus directly to each processor core instead of forwarding them through the HT interrupt line, increasing the flexibility of I/O interrupt usage.
 
 Before the core can use the extended I/O interrupt, it needs to enable the corresponding bit in the "`Other function configuration register`".
 This register has a base address of `0x1fe00000`,It can also be accessed using the configuration register instruction (IOCSR), an offset address of `0x0420`.
@@ -32,4 +32,4 @@ include::extended-io-interrupts/accessing-by-configuration-register-instructions
 
 include::extended-io-interrupts/extended-io-interrupt-trigger-register.adoc[]
 
-include::extended-io-interrupts/difference-in-handling-between-extended-io-interrupts-and-traditional-ht-interrupts.adoc[]
+include::extended-io-interrupts/difference-in-handling-between-extended-io-interrupts-and-legacy-ht-interrupts.adoc[]

docs/Loongson-3A5000-usermanual-EN/io-interrupts/extended-io-interrupts/accessing-by-address.adoc

@@ -152,9 +152,9 @@ d|Offset Address
 |Interrupt status of extended I/O interrupt `[255:192]` routed to processor core 3
 |===
 
-Similar to traditional I/O interrupts, the 256-bit interrupt source for Extended I/O interrupts can be software-configured to select the target processor core for the desired interrupt.
+Similar to legacy I/O interrupts, the 256-bit interrupt source for Extended I/O interrupts can be software-configured to select the target processor core for the desired interrupt.
 
-However, the interrupt sources are not individually selected to route to any of the processor core interrupts INT0 through INT3, but rather the routing of INT interrupts is done in groups. 
+However, the interrupt sources are not individually selected to route to any of the processor core interrupts INT0 through INT3, but rather the routing of INT interrupts is done in groups.
 The following are the interrupt pin routing registers configured by group.
 
 Starting with the 3A5000, the interrupt pin routing bits have been added in a coded manner and are enabled by the `CSR[0x420][49]` bit control.

docs/Loongson-3A5000-usermanual-EN/io-interrupts/extended-io-interrupts/difference-in-handling-between-extended-io-interrupts-and-traditional-ht-interrupts.adoc → docs/Loongson-3A5000-usermanual-EN/io-interrupts/extended-io-interrupts/difference-in-handling-between-extended-io-interrupts-and-legacy-ht-interrupts.adoc

@@ -1,15 +1,15 @@
-[[difference-in-handling-between-extended-io-interrupts-and-traditional-ht-interrupts]]
-==== Difference in Handling Between Extended I/O Interrupts and Traditional HT Interrupts
+[[difference-in-handling-between-extended-io-interrupts-and-legacy-ht-interrupts]]
+==== Difference in Handling Between Extended I/O Interrupts and Legacy HT Interrupts
 
-With traditional HT interrupt processing, HT interrupts are processed internally by the HT controller and mapped directly to the `256` interrupt vectors on the HT configuration registers, and then the `256` interrupt vectors are grouped to generate `4` or `8` interrupts that are routed to the various processor cores.
-Due to the traditional interrupt line connection, no cross-chip interrupts can be generated directly, so all HT I/O interrupts can only be handled directly by a single chip.
+With legacy HT interrupt processing, HT interrupts are processed internally by the HT controller and mapped directly to the `256` interrupt vectors on the HT configuration registers, and then the `256` interrupt vectors are grouped to generate `4` or `8` interrupts that are routed to the various processor cores.
+Due to the legacy interrupt line connection, no cross-chip interrupts can be generated directly, so all HT I/O interrupts can only be handled directly by a single chip.
 On the other hand, the interrupts distributed by the hardware within the chip are only in units of the final `4` or `8` interrupts and cannot be handled on a bit-by-bit basis, which leads to the problem of poor hardware interrupt distribution.
 
 With the extended I/O interrupt method, HT interrupts are sent directly from the HT controller to the chip's interrupt controller for processing, and the interrupt controller can directly get `256` Instead of the previous `4` or `8` interrupts, each of these 256-bit interrupts can be routed and distributed independently, and can be distributed and rotated across slices.
 
-With Extended I/O interrupts, the software processing is slightly different than with traditional HT interrupts.
+With Extended I/O interrupts, the software processing is slightly different than with legacy HT interrupts.
 
-With traditional HT interrupts, the kernel looks directly at the interrupt vector of the HT controller (typically `0x90000efdfb000080`) and then processes the interrupts by bit, regardless of how the routing mode is configured.
+With legacy HT interrupts, the kernel looks directly at the interrupt vector of the HT controller (typically `0x90000efdfb000080`) and then processes the interrupts by bit, regardless of how the routing mode is configured.
 
 After using Extended I/O interrupts, the cores go directly to the Extended I/O status register (configuration space `0x1800`) to read the interrupt status for processing.
 Each core will only read the interrupt's own interrupt status and process it, and there will be no interference between different cores.

docs/Loongson-3A5000-usermanual-EN/io-interrupts/traditional-io-interrupts.adoc → docs/Loongson-3A5000-usermanual-EN/io-interrupts/legacy-io-interrupts.adoc

@@ -1,5 +1,5 @@
-[[traditional-io-interrupts]]
-=== Traditional I/O Interrupts
+[[legacy-io-interrupts]]
+=== Legacy I/O Interrupts
 
 The legacy interrupts on the Loongson 3A5000 chip support `32` interrupt sources managed in a unified manner as shown in the figure below.
 Any of the I/O interrupt sources can be configured to enable or disable, how it is triggered, and the target processor core interrupt pin to be routed.
@@ -161,6 +161,6 @@ m|31:24
 
 Similar to inter-processor interrupts, the base address of I/O interrupts can also be accessed using `0x1fe00000`, or through the processor core's dedicated register configuration instructions.
 
-include::traditional-io-interrupts/accessing-by-address.adoc[]
+include::legacy-io-interrupts/accessing-by-address.adoc[]
 
-include::traditional-io-interrupts/accessing-by-configuration-register-instructions.adoc[]
+include::legacy-io-interrupts/accessing-by-configuration-register-instructions.adoc[]

docs/Loongson-3A5000-usermanual-EN/la464-processor-core/instruction-set-features-implemented-in-3a5000.adoc

@@ -4,8 +4,8 @@
 The functional features of the Loongson instruction set implemented in the Loongson 3A5000 can be dynamically confirmed by the Loongson instruction set attribute identification mechanism.
 
 The CPUCFG instruction is a user-state instruction, which is used as CPUCFG rd, rj, where the source operand rj register holds the register number of the configuration information word to be accessed, and the returned configuration word information is written to the rd register, each configuration information word contains up to 32 bits of configuration information.
- For example, bit 0 of configuration word 1 indicates whether the LA32 architecture is implemented, then this configuration information is expressed as CPUCFG.1.LA32[bit0], where 1 means that the font size of the configuration information word is 1, LA32 means that the helper name of this configuration information field is LA32, and bit 0 means that the field LA32 is located in bit 0 of the configuration word. 
- If the configuration information needs to be expressed in multiple bits, then the location information will be recorded in the form of bitAA:BB, which means the consecutive (AA-BB+1) bits from the AAth to the BBth bit of the configuration information word.
+For example, bit 0 of configuration word 1 indicates whether the LA32 architecture is implemented, then this configuration information is expressed as CPUCFG.1.LA32[bit0], where 1 means that the font size of the configuration information word is 1, LA32 means that the helper name of this configuration information field is LA32, and bit 0 means that the field LA32 is located in bit 0 of the configuration word.
+If the configuration information needs to be expressed in multiple bits, then the location information will be recorded in the form of bitAA:BB, which means the consecutive (AA-BB+1) bits from the AAth to the BBth bit of the configuration information word.
 
 The following table gives a list of configuration information for the instruction set functions implemented in the 3A5000.
 The last column, "`Possible Value`", indicates a possible value to be read from this register, but does not imply that this is the value to be read from the 3A5000 processor.

docs/Loongson-3A5000-usermanual-EN/low-speed-io-controller-configuration/spi-controller/guide-to-the-use-of-spi-dual-quad-mode.adoc

@@ -1,7 +1,7 @@
 [[guide-to-the-use-of-spi-dual-quad-mode]]
 ==== Guide to the Use of SPI Dual/Quad Mode
 
-In addition to the traditional single-wire mode, the SPI controller also supports two operating modes, dual mode and quad mode, for booting from the SPI FLASH.
+In addition to the legacy single-wire mode, the SPI controller also supports two operating modes, dual mode and quad mode, for booting from the SPI FLASH.
 The SPI controller can be put into dual mode by setting the `dual_io` register, and quad mode by setting the `quad_io` register.
 The configuration code for these two registers can be added to the first few instructions of the BIOS code, and then the controller will be pointed to the corresponding operating mode after the configuration is completed, which can improve the boot-up speed.
 

docs/Loongson-3A5000-usermanual-EN/software-clock-system.adoc

@@ -2,7 +2,7 @@
 == Software Clock System
 
 Several different levels of usage are defined in the Loongson 3A5000 processor for the clocks used by the system software.
-Inside the processor core are the traditional counter/compare registers, the stable counter registers, and the chip-level node counter registers.
+Inside the processor core are the legacy counter/compare registers, the stable counter registers, and the chip-level node counter registers.
 
 The following is introductions to stable counter and node counter.
 

docs/Loongson-3A5000-usermanual-EN/system-configuration-and-control/descriptions-of-pins.adoc

@@ -49,7 +49,7 @@ d!Description
 !CLKSEL[7:6]
 !`2'b00` indicates that PHY clock frequency is `1.6GHz`
 
-`2'b01` indicates that PHY clock frequency is `6.4GHz` 
+`2'b01` indicates that PHY clock frequency is `6.4GHz`
 
 `2'b10` Reserved
 

docs/Loongson-7A1000-usermanual-EN/bridge-configuration-register/ht-clock-enable-and-dma-routing-configuration.adoc

@@ -23,17 +23,17 @@ Size: `32` bits
 |R/W
 |Reserved
 
-|1	
-|ht_hi_clken	
+|1
+|ht_hi_clken
 |R/W
 |`HT` Controller `1` Clock Enable
 
 `0`: Turn off the clock
 
 `1`: Turn on the clock
 
-|0	
-|ht_lo_clken	
+|0
+|ht_lo_clken
 |R/W
 |HT Controller `0` Clock Enable
 
@@ -50,10 +50,10 @@ Default value: `000a_a800h`
 
 Size: `32` bits
 
-This register is used to configure the routing information for the device's DMA accesses (i.e., the destination processor for the `DMA` access and the HT controller through which it passes). 
-Since the HT bus only supports `40`-bit addresses and the processor space (and the DMA access space) supports `64`-bit addresses, the addresses need to be transformed before and after passing through the HT bus in order to preserve the address routing information. This feature requires two supports: 
+This register is used to configure the routing information for the device's DMA accesses (i.e., the destination processor for the `DMA` access and the HT controller through which it passes).
+Since the HT bus only supports `40`-bit addresses and the processor space (and the DMA access space) supports `64`-bit addresses, the addresses need to be transformed before and after passing through the HT bus in order to preserve the address routing information. This feature requires two supports:
 
-. the bridge chip stores the node number information in a certain number of bits of the HT bus address; 
+. the bridge chip stores the node number information in a certain number of bits of the HT bus address;
 
 . on the processor side, the node information is remapped to the processor's node bit field using the address translation function of the HT receive window.
 
@@ -68,17 +68,17 @@ The LS7A1000 implements the `DMA` access node number translation function, which
 |Read/Write
 |Description
 
-|31:16	
-|dma_dest_ht	
+|31:16
+|dma_dest_ht
 |R/W
-|`DMA` access destination node routing configuration. There are 16 nodes, each bit corresponds to a node number. `bit31-16` correspond to `DMA` accesses to nodes `15-0` respectively. 
+|`DMA` access destination node routing configuration. There are 16 nodes, each bit corresponds to a node number. `bit31-16` correspond to `DMA` accesses to nodes `15-0` respectively.
 
 `1`: Routed to HT controller `1`
 
 `0`: Routed to HT controller `0`
 
-|15:13	
-|dma_node_id_offset_ma pped	
+|15:13
+|dma_node_id_offset_ma pped
 |R/W
 |Address Offset of the mapped `DMA` access node number in the HT address space (relative to bit32).
 
@@ -102,8 +102,8 @@ This register determines the maximum address range for `DMA` accesses to a singl
 |R/W
 |Reserved
 
-|3:0	
-|dma_node_id_mask	
+|3:0
+|dma_node_id_mask
 |R/W
 |Node number mask for `DMA` accesses. This register determines the number of nodes that can be accessed by device `DMA` access.
 

docs/Loongson-7A1000-usermanual-EN/bridge-configuration-register/memory-capacity-configuration-register.adoc

@@ -1,7 +1,7 @@
 [[memory-capacity-configuration-register]]
 === Memory Capacity Configuration Register
 
-This set of registers is used to configure the capacity of the video memory. This register represents the mask of the memory BAR register, 0 means the corresponding bit of the memory BAR register is writable, 1 means not writable. 
+This set of registers is used to configure the capacity of the video memory. This register represents the mask of the memory BAR register, 0 means the corresponding bit of the memory BAR register is writable, 1 means not writable.
 The number of 1's represents the memory capacity. The default memory capacity is 256MB.
 
 Address Offset: `3838`-`383Bh`