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m7md5303/README.md

🦅⚡My name is Mohamed Khaled and this is my personal GitHub account.

==>>My Portfolio

Popular repositories Loading

  1. Digital-Signal-Processing-Unit Digital-Signal-Processing-Unit Public

    A DSP based on xilinix FPGA DSP (DSP48E1) with some extra combinational logic. The project was implemented using verilog. The design schematics including the implemented design was done through viv…

    Verilog 1

  2. SPI_slave-with-a-single-port-RAM SPI_slave-with-a-single-port-RAM Public

    SPI communication protocol is one of the most famous protocols. In this project a spi slave was implemented using verilog accompanied with a single port RAM.

    Verilog 1

  3. Single-cycle-Risk-v Single-cycle-Risk-v Public

    A single cycle risk-v processor ALU implemented using Verilog HDL

    Verilog

  4. ALS_Unit ALS_Unit Public

    An arithmetic logic shift unit that performs operations on its inputs including XORing, Multiplication and rotating implemented with verilog. The functionality was tested by a testbench simulated u…

    Verilog

  5. Gray_Counter Gray_Counter Public

    A 2-bit gray counter implemented with verilog in addition with a testbench

    Verilog

  6. S_S_D_C_C S_S_D_C_C Public

    A simple moore self driving car control system. The system is responsible for accelerating, decelerating or even braking up the car. It is also capable to provide a signal to lock or unlock the doo…

    Verilog