onchipmemory

Components for working with FPGA SRAM blocks (or Block RAMs or BRAMs, called "on-chip memory" or OCM here)

The core component here is DualPortBRAM, which is for inferring dual-port FPGA OCM (must be symmetric = with equal read/write widths). The template itself is for true dual-port OCM (both ports can read or write) but the FPGA synthesis tools should manage to infer simpler variants (e.g one port read only, other port read-write) if the appropriate signals are set to constants. Note that this component currently maps to a BlackBox (why?) and needs the DualPortBRAM.v while synthesizing the generated Verilog. Using it in Chisel emulation should work fine, as it contains a simple Chisel model approximating the same OCM behavior.

SRLQueue uses a hand-optimized shift-register-based queue (FIFO) from the Berkeley SCORE project. This should give less LUTRAM usage and better timing compared to Chisel's own Queue (although it costs more flip-flops, they are plentiful on modern FPGAs). The hand-optimized Verilog (Q_srl_oreg3_prefull_SIMPLE.v) must be included for synthesis.

FPGAQueue implements a queue (FIFO) that makes use of DualPortBRAM for creating larger queues. If the number of queue elements is smaller than a threshold (currently 64 elements), an SRLQueue is created instead.

Note that neither of these queues support first word fall through (in Chisel queue-speak, pipe=false and flow=false). The ready-valid signals on enqueue-dequeue sides are decoupled.

TODO:

• support inference for asymmetric dual-port BRAMs
• support cascading multiple BRAMs with multi-cycle read/write completion for higher clock freq.
• add a better Chisel model for the SRLQueue to make co-debug easier
• rewrite OCMController (or backport from [here] (https://github.com/maltanar/seyrek/blob/master/src/main/scala/contextmem/BRAMContextMem.scala) to support init/flush with ext.mem. access