Xband NBAJAM Sync Method

; vbl synchronization
; vbls are synchronized each time vbl interrupts are enabled (except in local mode
; when vbl interrupts free run). vbls are considered to be in sync when:

; 1) they are in-phase. in-phase is determined by the master sending an echo message
; and receiving a reply in an even number of frame times. out of phase is bad
; because the latency in each direction is not equal.
;
; 2) their time-stamps are matched within syncjitter tolerance. this constraint is actually
; unnecessary for reliable operation, but it is a simplification during development.
; eventually, we’ll eliminate it for faster average sync-up time (albeit same
; worst-case).
;
; the current protocol works as follows:
;
; master:
; mode 0:
; txs a timestamp in a byte, rxs timestamps from slave. if turning on interlace
; will bring it into adjustment faster than the slave turning on interlace, it
; turns on interlace. presumably the slave is making the opposite evaluation at
; the same time. keeps going until timestamps are within syncjitter tolerance.
; it waits until it gets syncsneededinarow within tolerance and txs an echobyte
; and goes to mode 1.
;
; mode 1:
; counts frames until receives an echobyte and stores in latencycount. if it is an odd number,
; then it goes to mode 2. if it is an even number, it divides it by 2 and sends
; it to the slave with synclock1. it then goes to mode 3.
;
; mode 2:
; counts down 262 frames in interlace mode to go 180? out of phase. goes to mode 0.
;
; mode 3:
; it waits latencycount frames for the slave to get the message. then it sends a
; two byte echo message and goes to mode 6.
;
; mode 6:
; counts frames until is receives two echobytes and stores 1/2 latency in
; latencycount. sends a synclock2 with latency, goes to mode 7.
;
; mode 7:
; it waits latencycount frames for the slave to get the message. then it goes to
; moderun
;
;
; slave:
; mode 4:
; sends lasttimestamp. if it rxs data, and it is an echobyte, sends an echobyte back.
; if it is a timestamp, it evaluates whether turning on interlace
; will bring it into adjustment faster than the master turning on interlace. if so, it
; turns on interlace. if a synclock1 is rxed, it grabs the latencycount data, and
; goes to mode 8.
;
; mode 8:
; sends back echo message. when receives synclock2, waits latency frames and goes to
; moderun.
;
; master and slave:
;
; moderun (-1):
; rx data
; if rxdata is late
; go into (or stay in) interlaced mode to delay next read
; else
; go into (or stay in) non-int mode
;
; if rxdata is not nodata
; put into rxfifo
;
; if rxfifo is empty
; send nodata
; skip this vbl
; else
; if syncflag is zero (i.e. the game loop completed by vbl)
; read controllers
; tx read data
; set syncflag
; do the vbl
; else
; send nodata
; skip this vbl
;