next commit

Signed-off-by: Nathaniel Mitchell <[email protected]>

chipsec/cfg/parsers/core_parsers.py

@@ -27,17 +27,17 @@
 from chipsec.cfg.parsers.ip.msgbus import MSGBUSConfig
 from chipsec.cfg.parsers.ip.msr import MSRConfig
 from chipsec.cfg.parsers.ip.pci_device import PCIConfig
-from chipsec.cfg.parsers.registers.controls import CONTROLHelper
-from chipsec.cfg.parsers.registers.io import IORegisters
-from chipsec.cfg.parsers.registers.iobar import IOBARRegisters
-from chipsec.cfg.parsers.registers.memory import MEMORYRegisters
-from chipsec.cfg.parsers.registers.mm_msgbus import MM_MSGBUSRegisters
-from chipsec.cfg.parsers.registers.mmcfg import MMCFGRegisters
-from chipsec.cfg.parsers.registers.mmio import MMIORegisters
-from chipsec.cfg.parsers.registers.msgbus import MSGBUSRegisters
-from chipsec.cfg.parsers.registers.msr import MSRRegisters
-from chipsec.cfg.parsers.registers.pci import PCIRegisters
-from chipsec.cfg.parsers.registers.locks import LOCKSHelper
+from chipsec.cfg.parsers.controls import CONTROLHelper
+from chipsec.cfg.parsers.locks import LOCKSHelper
+from chipsec.cfg.parsers.registers.io import IORegisters #
+from chipsec.cfg.parsers.registers.iobar import IOBARRegisters #
+from chipsec.cfg.parsers.registers.memory import MEMORYRegisters #
+from chipsec.cfg.parsers.registers.mm_msgbus import MM_MSGBUSRegisters #
+from chipsec.cfg.parsers.registers.mmcfg import MMCFGRegisters #
+from chipsec.cfg.parsers.registers.mmio import MMIORegisters #
+from chipsec.cfg.parsers.registers.msgbus import MSGBUSRegisters #
+from chipsec.cfg.parsers.registers.msr import MSRRegisters #
+from chipsec.cfg.parsers.registers.pci import PCIRegisters #pcicfg
 from chipsec.parsers import BaseConfigParser
 from chipsec.parsers import Stage
 from chipsec.parsers import info_data, config_data

chipsec/config.py

@@ -528,21 +528,8 @@ def get_mmio_def(self, bar_name):
                 ret = self.MMIO_BARS[vid][device][bar]
         return ret
 
-    def get_io_def(self, bar_name):
-        scope = self.get_scope(bar_name)
-        vid, device, bar, _ = self.convert_internal_scope(scope, bar_name)
-        if bar in self.IO_BARS[vid][device]:
-            return self.IO_BARS[vid][device][bar]
-        else:
-            return None
 
-    def get_mem_def(self, range_name):
-        scope = self.get_scope(range_name)
-        vid, range, _, _ = self.convert_internal_scope(scope, range_name)
-        if range in self.MEMORY_RANGES[vid]:
-            return self.MEMORY_RANGES[vid][range]
-        else:
-            return None
+
 
     def get_device_bus(self, dev_name):
         scope = self.get_scope(dev_name)

chipsec/hal/physmem.py

@@ -29,9 +29,10 @@
 """
 
 from struct import unpack, pack
-from typing import Tuple, Optional
+from typing import Any, Dict, Tuple, Optional
 from chipsec.hal.hal_base import HALBase
 from chipsec.library.logger import print_buffer_bytes
+from chipsec.library.bits import make_mask
 
 
 class Memory(HALBase):
@@ -163,10 +164,16 @@ def get_max_memory_bit_size(self):
 
     def get_max_memory_mask(self):
         size = self.get_max_memory_bit_size()
-        return self.get_bit_mask(size)
+        return make_mask(size)
 
-    def get_bit_mask(self, size):
-        return (1 << size) - 1
 
     def get_value_from_bit_def(self, inputValue, fieldStartBit, fieldSize):
         return (inputValue >> fieldStartBit) & self.get_bit_mask(fieldSize)
+
+    def get_def(self, range_name: str) -> Dict[str, Any]:
+        '''Return address access of a MEM register'''
+        scope = self.cs.Cfg.get_scope(range_name)
+        vid, range, _, _ = self.cs.Cfg.convert_internal_scope(scope, range_name)
+        if vid in self.cs.Cfg.MEMORY_RANGES and range in self.cs.Cfg.MEMORY_RANGES[vid]:
+            return self.cs.Cfg.MEMORY_RANGES[vid][range]
+        return None