Merge pull request #324 from silabs-oysteink/silabs-oysteink_merge-w41

Merge from CV32E40X
openhwgroup · Oct 12, 2022 · 3462ed2 · 3462ed2
2 parents 0ac403b + 5a41c42
commit 3462ed2
Show file tree

Hide file tree

Showing 4 changed files with 27 additions and 13 deletions.
diff --git a/docs/user_manual/source/control_status_registers.rst b/docs/user_manual/source/control_status_registers.rst
@@ -1385,7 +1385,7 @@ Scratch swap register for multiple privilege modes.
 
 .. note::
   Only the read-modify-write (swap/CSRRW) operation is useful for ``mscratchcsw``.
-  The behavior of the non-CSRRW variants (i.e. CSRRS/C, CSRRWI, CSRRS/CI) and CSRRW variants with **rd** = **x0** on ``mscratchcsw`` are implementation-defined.
+  The behavior of the non-CSRRW variants (i.e. CSRRS/C, CSRRWI, CSRRS/CI) and CSRRW variants with **rd** = **x0** or **rs1** = **x0** on ``mscratchcsw`` are implementation-defined.
   |corev| will treat such instructions as illegal instructions.
 
 .. _csr-mscratchcswl:
@@ -1415,7 +1415,7 @@ Scratch swap register for multiple interrupt levels.
 
 .. note::
   Only the read-modify-write (swap/CSRRW) operation is useful for ``mscratchcswl``.
-  The behavior of the non-CSRRW variants (i.e. CSRRS/C, CSRRWI, CSRRS/CI) and CSRRW variants with **rd** = **x0** on ``mscratchcswl`` are implementation-defined.
+  The behavior of the non-CSRRW variants (i.e. CSRRS/C, CSRRWI, CSRRS/CI) and CSRRW variants with **rd** = **x0** or **rs1** = **x0** on ``mscratchcswl`` are implementation-defined.
   |corev| will treat such instructions as illegal instructions.
 
 .. _csr-mclicbase:
@@ -1586,7 +1586,7 @@ Reset Value: Not applicable
   +-------+--------------+----------------------------------------------------------------+
   | 11    | WARL (0x0)   | **VU**. Hardwired to 0.                                        |
   +-------+--------------+----------------------------------------------------------------+
-  | 10    | WARL         | **NMI**. Set to enable trigger on NMI.                         |
+  | 10    | WARL (0x0)   | Hardwired to 0.                                                |
   +-------+--------------+----------------------------------------------------------------+
   | 9     | WARL         | **M**. Match in machine mode.                                  |
   +-------+--------------+----------------------------------------------------------------+
@@ -1623,7 +1623,6 @@ Reset Value: Not applicable
   | 26:0  | WARL (0x0)  | **DATA**.                                                      |
   +-------+-------------+----------------------------------------------------------------+
 
-
 .. _csr-tdata2:
 
 Trigger Data Register 2 (``tdata2``)
@@ -1646,7 +1645,7 @@ Detailed:
   +-------+------+------------------------------------------------------------------+
 
 Accessible in Debug Mode or M-Mode, depending on **tdata1.dmode**.
-This register stores the instruction address to match against for a breakpoint trigger or the currently selected exception codes for an exception trigger.
+This register stores the instruction address, load address or store address to match against for a breakpoint trigger or the currently selected exception codes for an exception trigger.
 
 .. _csr-tdata3:
 

diff --git a/rtl/cv32e40s_cs_registers.sv b/rtl/cv32e40s_cs_registers.sv
@@ -165,6 +165,7 @@ module cv32e40s_cs_registers import cv32e40s_pkg::*;
 
   logic                         illegal_csr_read;                               // Current CSR cannot be read
   logic                         illegal_csr_write;                              // Current CSR cannot be written
+  logic                         illegal_csr_instr;                              // Current CSR cannot be accessed with the current instruction (mscratchcsw[l] with non-csrrw)
 
   logic                         instr_valid;                                    // Local instr_valid
 
@@ -442,7 +443,10 @@ module cv32e40s_cs_registers import cv32e40s_pkg::*;
   // Any access to JVT is only legal from machine mode, or from user mode when mstateen[2] is 1.
   assign illegal_jvt_access = ((csr_raddr == CSR_JVT) && ((id_ex_pipe_i.priv_lvl < PRIV_LVL_M) && !mstateen0_rdata[2]));
 
-  assign csr_illegal_o = (id_ex_pipe_i.instr_valid && id_ex_pipe_i.csr_en) ? illegal_csr_write || illegal_csr_read || illegal_csr_read_priv || illegal_jvt_access : 1'b0;
+  // Flag illegal instruction if accessing mscratchcsw[l] with non-csrrw instruction or csrrw with rd==x0
+
+  assign illegal_csr_instr = ((csr_raddr == CSR_MSCRATCHCSW) || (csr_raddr == CSR_MSCRATCHCSWL)) && !(id_ex_pipe_i.csr_op == CSR_OP_CSRRW);
+  assign csr_illegal_o = (id_ex_pipe_i.instr_valid && id_ex_pipe_i.csr_en) ? illegal_csr_write || illegal_csr_read || illegal_csr_read_priv || illegal_jvt_access || illegal_csr_instr: 1'b0;
 
 
   ////////////////////////////////////////////
@@ -1616,8 +1620,10 @@ module cv32e40s_cs_registers import cv32e40s_pkg::*;
       csr_we_int    = 1'b0;
     end else begin
       csr_we_int    = 1'b1;
+      csr_wdata_int = csr_wdata;
       case (csr_op)
-        CSR_OP_WRITE: csr_wdata_int = csr_wdata;
+        CSR_OP_WRITE,
+        CSR_OP_CSRRW: csr_wdata_int = csr_wdata;
         CSR_OP_SET:   csr_wdata_int = csr_wdata | ex_wb_pipe_i.rf_wdata;
         CSR_OP_CLEAR: csr_wdata_int = (~csr_wdata) & ex_wb_pipe_i.rf_wdata;
 
@@ -2084,6 +2090,7 @@ module cv32e40s_cs_registers import cv32e40s_pkg::*;
   assign csr_wr_in_wb = ex_wb_pipe_i.csr_en &&
                         ex_wb_pipe_i.instr_valid &&
                         ((csr_op == CSR_OP_WRITE) ||
+                         (csr_op == CSR_OP_CSRRW) ||
                          (csr_op == CSR_OP_SET)   ||
                          (csr_op == CSR_OP_CLEAR));
 

diff --git a/rtl/cv32e40s_i_decoder.sv b/rtl/cv32e40s_i_decoder.sv
@@ -379,7 +379,14 @@ module cv32e40s_i_decoder import cv32e40s_pkg::*;
           // instr_rdata_i[19:14] = rs or immediate value
           // If set or clear with rs==x0 or imm==0, then do not perform a write action
           unique case (instr_rdata_i[13:12])
-            2'b01:   decoder_ctrl_o.csr_op = CSR_OP_WRITE;
+            2'b01: begin
+              // Detect true CSRRW with rd != x0 for use with mscratchcsw[l] accesses
+              if ((instr_rdata_i[14] != 1'b1) && (instr_rdata_i[11:7] != 5'b0) && (instr_rdata_i[19:15] != 5'b0)) begin
+                decoder_ctrl_o.csr_op = CSR_OP_CSRRW;
+              end else begin
+                decoder_ctrl_o.csr_op = CSR_OP_WRITE;
+              end
+            end
             2'b10:   decoder_ctrl_o.csr_op = (instr_rdata_i[19:15] == 5'b0) ? CSR_OP_READ : CSR_OP_SET;
             2'b11:   decoder_ctrl_o.csr_op = (instr_rdata_i[19:15] == 5'b0) ? CSR_OP_READ : CSR_OP_CLEAR;
             default: decoder_ctrl_o = DECODER_CTRL_ILLEGAL_INSN;

diff --git a/rtl/include/cv32e40s_pkg.sv b/rtl/include/cv32e40s_pkg.sv
@@ -488,14 +488,15 @@ parameter CSR_MSTATEEN0_MASK    = 32'h00000004;
 
 // CSR operations
 
-parameter CSR_OP_WIDTH = 2;
+parameter CSR_OP_WIDTH = 3;
 
 typedef enum logic [CSR_OP_WIDTH-1:0]
 {
- CSR_OP_READ  = 2'b00,
- CSR_OP_WRITE = 2'b01,
- CSR_OP_SET   = 2'b10,
- CSR_OP_CLEAR = 2'b11
+ CSR_OP_READ  = 3'b000,
+ CSR_OP_WRITE = 3'b001,
+ CSR_OP_SET   = 3'b010,
+ CSR_OP_CLEAR = 3'b011,
+ CSR_OP_CSRRW = 3'b100
 } csr_opcode_e;
 
 // CSR interrupt pending/enable bits