Skip to content

Commit

Permalink
Merge pull request #222 from silabs-oysteink/silabs-oysteink_smstateen
Browse files Browse the repository at this point in the history 
Implemented Smstateen for table jumps
  • Loading branch information
@Silabs-ArjanB
Silabs-ArjanB authored Jun 7, 2022
2 parents e7586fa + b28c224 commit 6c41ac9
Show file tree
Hide file tree
Showing 8 changed files with 273 additions and 66 deletions.
45 changes: 24 additions & 21 deletions bhv/cv32e40s_wrapper.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -629,27 +629,30 @@ module cv32e40s_wrapper
.csr_secureseed2_n_i ( core_i.cs_registers_i.secureseed2_n ),
.csr_secureseed2_q_i ( core_i.cs_registers_i.secureseed2_rdata ),
.csr_secureseed2_we_i ( core_i.cs_registers_i.secureseed2_we ),
.csr_mstateen0_n_i ( '0 /* TODO: connect */ ),
.csr_mstateen0_q_i ( '0 /* TODO: connect */ ),
.csr_mstateen0_we_i ( '0 /* TODO: connect */ ),
.csr_mstateen1_n_i ( '0 /* TODO: connect */ ),
.csr_mstateen1_q_i ( '0 /* TODO: connect */ ),
.csr_mstateen1_we_i ( '0 /* TODO: connect */ ),
.csr_mstateen2_n_i ( '0 /* TODO: connect */ ),
.csr_mstateen2_q_i ( '0 /* TODO: connect */ ),
.csr_mstateen2_we_i ( '0 /* TODO: connect */ ),
.csr_mstateen0h_n_i ( '0 /* TODO: connect */ ),
.csr_mstateen0h_q_i ( '0 /* TODO: connect */ ),
.csr_mstateen0h_we_i ( '0 /* TODO: connect */ ),
.csr_mstateen1h_n_i ( '0 /* TODO: connect */ ),
.csr_mstateen1h_q_i ( '0 /* TODO: connect */ ),
.csr_mstateen1h_we_i ( '0 /* TODO: connect */ ),
.csr_mstateen2h_n_i ( '0 /* TODO: connect */ ),
.csr_mstateen2h_q_i ( '0 /* TODO: connect */ ),
.csr_mstateen2h_we_i ( '0 /* TODO: connect */ )
.csr_mstateen3h_n_i ( '0 /* TODO: connect */ ),
.csr_mstateen3h_q_i ( '0 /* TODO: connect */ ),
.csr_mstateen3h_we_i ( '0 /* TODO: connect */ )
.csr_mstateen0_n_i ( core_i.cs_registers_i.mstateen0_n ),
.csr_mstateen0_q_i ( core_i.cs_registers_i.mstateen0_rdata ),
.csr_mstateen0_we_i ( core_i.cs_registers_i.mstateen0_we ),
.csr_mstateen1_n_i ( core_i.cs_registers_i.mstateen1_n ),
.csr_mstateen1_q_i ( core_i.cs_registers_i.mstateen1_rdata ),
.csr_mstateen1_we_i ( core_i.cs_registers_i.mstateen1_we ),
.csr_mstateen2_n_i ( core_i.cs_registers_i.mstateen2_n ),
.csr_mstateen2_q_i ( core_i.cs_registers_i.mstateen2_rdata ),
.csr_mstateen2_we_i ( core_i.cs_registers_i.mstateen2_we ),
.csr_mstateen3_n_i ( core_i.cs_registers_i.mstateen3_n ),
.csr_mstateen3_q_i ( core_i.cs_registers_i.mstateen3_rdata ),
.csr_mstateen3_we_i ( core_i.cs_registers_i.mstateen3_we ),
.csr_mstateen0h_n_i ( core_i.cs_registers_i.mstateen0h_n ),
.csr_mstateen0h_q_i ( core_i.cs_registers_i.mstateen0h_rdata ),
.csr_mstateen0h_we_i ( core_i.cs_registers_i.mstateen0h_we ),
.csr_mstateen1h_n_i ( core_i.cs_registers_i.mstateen1h_n ),
.csr_mstateen1h_q_i ( core_i.cs_registers_i.mstateen1h_rdata ),
.csr_mstateen1h_we_i ( core_i.cs_registers_i.mstateen1h_we ),
.csr_mstateen2h_n_i ( core_i.cs_registers_i.mstateen2h_n ),
.csr_mstateen2h_q_i ( core_i.cs_registers_i.mstateen2h_rdata ),
.csr_mstateen2h_we_i ( core_i.cs_registers_i.mstateen2h_we ),
.csr_mstateen3h_n_i ( core_i.cs_registers_i.mstateen3h_n ),
.csr_mstateen3h_q_i ( core_i.cs_registers_i.mstateen3h_rdata ),
.csr_mstateen3h_we_i ( core_i.cs_registers_i.mstateen3h_we )


`ifdef RISCV_FORMAL
Expand Down
7 changes: 6 additions & 1 deletion rtl/cv32e40s_compressed_decoder.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,8 @@ module cv32e40s_compressed_decoder import cv32e40s_pkg::*;
(
input inst_resp_t instr_i,
input logic instr_is_ptr_i,
input logic [31:0] mstateen0_i,
input privlvl_t priv_lvl_i,
output inst_resp_t instr_o,
output logic is_compressed_o,
output logic illegal_instr_o,
Expand Down Expand Up @@ -439,7 +441,10 @@ module cv32e40s_compressed_decoder import cv32e40s_pkg::*;
end

3'b101: begin
if (ZC_EXT) begin
// Table jumps are only allowed while in machine mode, or in user mode when mstateen0[2] = 1
// mstateen0 is only writeable from machine mode, and thus it is safe to use it directly with no
// hazard detection or stalls (an mret would need to be executed after the CSR write to enter user mode)
if (ZC_EXT && ((priv_lvl_i == PRIV_LVL_M) || mstateen0_i[2])) begin
// The cm.jt and cm.jalt have no equivalent 32-bit instructions.
// Mapping to JAL anyway, but an extra control bit is set to indicate that these
// are table jumps as opposed to regular JAL instruction.
Expand Down
4 changes: 4 additions & 0 deletions rtl/cv32e40s_core.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -218,6 +218,8 @@ module cv32e40s_core import cv32e40s_pkg::*;

logic [MTVT_ADDR_WIDTH-1:0] mtvt_addr;

logic [31:0] mstateen0;

logic [7:0] mintthresh;
mintstatus_t mintstatus;

Expand Down Expand Up @@ -532,6 +534,7 @@ module cv32e40s_core import cv32e40s_pkg::*;

// CSR registers
.csr_pmp_i ( csr_pmp ),
.mstateen0_i ( mstateen0 ),

// Privilege level
.priv_lvl_ctrl_i ( priv_lvl_if_ctrl ),
Expand Down Expand Up @@ -849,6 +852,7 @@ module cv32e40s_core import cv32e40s_pkg::*;
.mtvec_addr_o ( mtvec_addr ),
.mtvec_mode_o ( mtvec_mode ),
.mtvt_addr_o ( mtvt_addr ),
.mstateen0_o ( mstateen0 ),

.priv_lvl_if_ctrl_o ( priv_lvl_if_ctrl ),
.priv_lvl_lsu_o ( priv_lvl_lsu ),
Expand Down
Loading

0 comments on commit 6c41ac9

Please sign in to comment.