Merge pull request #518 from silabs-oysteink/silabs-oysteink_merge-w4…

…2.23-1 Merge from c32e40x
openhwgroup · Oct 17, 2023 · d45d7b4 · d45d7b4
2 parents 3db0d0d + 4c6eba7
commit d45d7b4
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diff --git a/docs/user_manual/source/control_status_registers.rst b/docs/user_manual/source/control_status_registers.rst
@@ -933,9 +933,11 @@ Detailed:
     +------+-------------+---------------------------------------------------------------+
     | Bit# |  R/W        | Definition                                                    |
     +======+=============+===============================================================+
-    | 31   | R (0x0)     | **STCE**. Hardwired to 0                                      |
+    | 31   | WARL (0x0)  | **STCE**. Hardwired to 0                                      |
     +------+-------------+---------------------------------------------------------------+
-    | 30:0 | WPRI (0x0)  | Reserved. Hardwired to 0.                                     |
+    | 30   | WARL (0x0)  | **PBMTE**. Hardwired to 0                                     |
+    +------+-------------+---------------------------------------------------------------+
+    | 29:0 | WPRI (0x0)  | Reserved. Hardwired to 0.                                     |
     +------+-------------+---------------------------------------------------------------+
 
   Machine State Enable 0 (``mstateen0h``)

diff --git a/docs/user_manual/source/intro.rst b/docs/user_manual/source/intro.rst
@@ -36,14 +36,14 @@ It follows these specifications:
 .. [RISC-V-UNPRIV] RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213 (December 13, 2019),
    https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
 
-.. [RISC-V-PRIV] RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211105-signoff (November 5, 2021),
-   https://github.com/riscv/riscv-isa-manual/releases/download/draft-20211105-c30284b/riscv-privileged.pdf
+.. [RISC-V-PRIV] RISC-V Instruction Set Manual, Volume II: Privileged Architecture, Document Version 20211203 (December 4, 2021),
+   https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf
 
 .. [RISC-V-RV32E] RISC-V Instruction Set Manual, Volume I: User-Level ISA, RV32E Base Integer Instruction Set, Document version 20191214-draft (January 31, 2023),
    https://github.com/riscv/riscv-isa-manual/releases/download/draft-20230131-c0b298a/riscv-spec.pdf
 
-.. [RISC-V-DEBUG] RISC-V Debug Support, version 1.0-STABLE, 27d602966ae72e70568e4951ab90c393a6930ae4, September 11 2023,
-   https://github.com/riscv/riscv-debug-spec/blob/2c8f38a0a46cd07f908057c5463c4b6810462146/riscv-debug-stable.pdf
+.. [RISC-V-DEBUG] RISC-V Debug Support, version 1.0-STABLE, f5b2ed3bb0eefcca075e99f3a8eece06e8d60063, October 12 2023,
+   https://github.com/riscv/riscv-debug-spec/blob/51f5a29c0126d69f314079fb4f1197876aca7622/riscv-debug-stable.pdf
 
 .. [RISC-V-CLIC] Core-Local Interrupt Controller (CLIC) RISC-V Privileged Architecture Extensions, version 0.9-draft, 9/1/2023,
    https://github.com/riscv/riscv-fast-interrupt/blob/894a16ce89dcf2c084dd951866448c2e756d3efa/clic.pdf

diff --git a/yaml/csr.yaml.m4 b/yaml/csr.yaml.m4
@@ -5073,12 +5073,19 @@ ifelse(eval(UMODE != 0), 1, [[[
       reset_val: 0
       msb: 31
       lsb: 31
+    - field_name: PBMTE
+      description: >
+        Hardwired to 0
+      type: R
+      reset_val: 0
+      msb: 30
+      lsb: 30
     - field_name: RESERVED0
       description: >
         Hardwired to 0
       type: WPRI
       reset_val: 0
-      msb: 30
+      msb: 29
       lsb: 0
 ]]])