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Merge pull request #1238 from jordancarlin/zc_tests
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Update riscv-arch-test and enable remaining Zcf and Zcd tests
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davidharrishmc authored Jan 22, 2025
2 parents 94845dc + e0c4eee commit 5c4e2ea
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Showing 4 changed files with 8 additions and 11 deletions.
2 changes: 1 addition & 1 deletion addins/riscv-arch-test
Submodule riscv-arch-test updated 318 files
11 changes: 4 additions & 7 deletions testbench/tests.vh
Original file line number Diff line number Diff line change
Expand Up @@ -537,7 +537,6 @@ string arch64cpriv[] = '{
"rv64i_m/C/src/cebreak-01.S"
};

// Tests commented out pending riscv-arch-test issue #590
string arch64zcd[] = '{
// `RISCVARCHTEST,
"rv64i_m/D_Zcd/src/c.fld-01.S",
Expand Down Expand Up @@ -3431,20 +3430,18 @@ string arch32cpriv[] = '{
"rv32i_m/C/src/cebreak-01.S"
};

// Tests commented out pending riscv-arch-test issue #590
string arch32zcf[] = '{
// `RISCVARCHTEST,
// "rv32i_m/F_Zcf/src/c.flw-01.S",
// "rv32i_m/F_Zcf/src/c.flwsp-01.S",
// "rv32i_m/F_Zcf/src/c.fsw-01.S",
"rv32i_m/F_Zcf/src/c.flw-01.S",
"rv32i_m/F_Zcf/src/c.flwsp-01.S",
"rv32i_m/F_Zcf/src/c.fsw-01.S",
"rv32i_m/F_Zcf/src/c.fswsp-01.S"
};

// Tests commented out pending riscv-arch-test issue #590
string arch32zcd[] = '{
// `RISCVARCHTEST,
"rv32i_m/D_Zcd/src/c.fld-01.S",
// "rv32i_m/D_Zcd/src/c.fldsp-01.S",
"rv32i_m/D_Zcd/src/c.fldsp-01.S",
"rv32i_m/D_Zcd/src/c.fsd-01.S",
"rv32i_m/D_Zcd/src/c.fsdsp-01.S"
};
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4 changes: 2 additions & 2 deletions tests/riscof/spike/spike_rv32gc_isa.yaml
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
hart_ids: [0]
hart0:
# ISA: RV32IMAFDCZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV32IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zcf_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]
Expand All @@ -26,4 +26,4 @@ hart0:
legal:
- extensions[25:0] bitmask [0x014112D, 0x0000000]
wr_illegal:
- Unchanged
- Unchanged
2 changes: 1 addition & 1 deletion tests/riscof/spike/spike_rv64gc_isa.yaml
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
hart_ids: [0]
hart0:
# ISA: RV64IMAFDQCSUZicboz_Zicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
ISA: RV64IMAFDCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zcd_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
# ISA: RV64IMAFDQCSUZicsr_Zicond_Zifencei_Zfa_Zfh_Zca_Zcb_Zba_Zbb_Zbc_Zbkb_Zbkc_Zbkx_Zbs_Zknd_Zkne_Zknh
physical_addr_sz: 56
User_Spec_Version: '2.3'
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