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Aryan softplus #24378

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Aryan softplus #24378

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f8e620b
Fix the issue #24114
Aryan8912 Apr 28, 2024
c2a967d
Implement CPU plugin just-in-time emitter for SoftPlus operation #24109
Aryan8912 May 6, 2024
81b9151
Implement CPU plugin just-in-time emitter for SoftPlus operation #24109
Aryan8912 May 6, 2024
b29541b
Update softplus function
Aryan8912 May 13, 2024
e98f33e
Merge branch 'master' into aryan_softplus
Aryan8912 May 14, 2024
e55d6aa
Update jit_eltwise_emitters.cpp
Aryan8912 May 16, 2024
782913c
Update jit_eltwise_emitters.hpp
Aryan8912 May 16, 2024
2f72cab
Update jit_eltwise_emitters.cpp
Aryan8912 May 16, 2024
931cf4f
Merge branch 'master' into aryan_softplus
Aryan8912 May 16, 2024
7a60487
Update jit_eltwise_emitters.cpp
Aryan8912 May 20, 2024
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49 changes: 49 additions & 0 deletions src/plugins/intel_cpu/src/emitters/plugin/aarch64/jit_eltwise_emitters.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -896,6 +896,55 @@ void jit_select_emitter::emit_isa(const std::vector<size_t> &in_vec_idxs, const
h->mov(dst.b16, aux.b16);
}

// SoftPlus
jit_soft_plus_emitter::jit_soft_plus_emitter(dnnl::impl::cpu::aarch64::jit_generator* host,
dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
const std::shared_ptr<ov::Node>& node)
: jit_emitter(host, host_isa, node, get_arithmetic_binary_exec_precision(node)) {
}
jit_soft_plus_emitter::jit_soft_plus_emitter(dnnl::impl::cpu::aarch64::jit_generator* host,
dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
const ov::element::Type exec_prc)
: jit_emitter(host, host_isa, exec_prc) {
}
size_t jit_soft_plus_emitter::get_inputs_count() const { return 1; }
size_t jit_soft_plus_emitter::get_aux_vecs_count() const { return 1; }

std::set<std::vector<element::Type>> jit_soft_plus_emitter::get_supported_precisions(const std::shared_ptr<ov::Node>& node) {
return {{element::f32}};
}

void jit_soft_plus_emitter::emit_impl(const std::vector<size_t>& in_vec_idxs, const std::vector<size_t>& out_vec_idxs) const {
if (host_isa_ == dnnl::impl::cpu::aarch64::asimd) {
emit_isa<dnnl::impl::cpu::aarch64::asimd>(in_vec_idxs, out_vec_idxs);
} else {
OV_CPU_JIT_EMITTER_THROW("Can't create jit eltwise kernel");
}
}

template <dnnl::impl::cpu::aarch64::cpu_isa_t isa>
void jit_soft_plus_emitter::emit_isa(const std::vector<size_t> &in_vec_idxs, const std::vector<size_t> &out_vec_idxs) const {
OV_CPU_JIT_EMITTER_ASSERT(exec_prc_ == ov::element::f32, "unsupported precision: " + exec_prc_.to_string());
using TReg = typename dnnl::impl::cpu::aarch64::cpu_isa_traits<isa>::TReg;
const TReg src = TReg(in_vec_idxs[0]);
const TReg dst = TReg(out_vec_idxs[0]);
const TReg aux = TReg(aux_vec_idxs[0]);
h->vldr(src.d, v0.d);
h->vmul(dst.d, v0.d, v0.d);
h->vcvt(dst.s, dst.d);
h->vfma(dst.s, v0.s, vptrue, v1.s, dst.s);
h->vmaxnm(dst.s, dst.s, vmmin.s);
h->vcvt(dst.d, dst.s);
h->vexp2(dst.d, dst.d);
h->vadd(dst.d, dst.d, vone.d);
h->vrcps(dst.d, dst.d);
h->vrsqrts(dst.d, dst.d);
h->vadd(dst.d, dst.d, vzero.d);
h->vst1(dst.d, ptr[dst_reg]);
Comment on lines +932 to +943
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  1. You don't need to load anything in emitter. By the main concept: everything has been loaded in vector registers already, use registers.
  2. Inside emitter you can use only in_vec_idxs, out_vec_idxs and aux_vec_idxs vector registers (their indexes).
  3. In float implementation use word only.
  4. Use instrucations from SIMD&FP Instructions from ARM64 instruction set. We don't support ARM32 in OpenVINO snippets.

Note, please, you can use PRs as example:

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Hey @eshoguli please tell me more details about this, I am busy with other things

}
}


/// SIGMOID ///
jit_sigmoid_emitter::jit_sigmoid_emitter(dnnl::impl::cpu::aarch64::jit_generator* host,
dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
Expand Down
23 changes: 23 additions & 0 deletions src/plugins/intel_cpu/src/emitters/plugin/aarch64/jit_eltwise_emitters.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -377,6 +377,29 @@ class jit_select_emitter : public jit_emitter {
void emit_isa(const std::vector<size_t> &in_vec_idxs, const std::vector<size_t> &out_vec_idxs) const;
};

class jit_soft_plus_emitter : public jit_emitter {
public:
jit_soft_plus_emitter(dnnl::impl::cpu::aarch64::jit_generator *host,
dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
const ov::element::Type exec_prc = ov::element::f32);

jit_soft_plus_emitter(dnnl::impl::cpu::aarch64::jit_generator *host,
dnnl::impl::cpu::aarch64::cpu_isa_t host_isa,
const std::shared_ptr<ov::Node>& node);

size_t get_inputs_count() const override;
size_t get_aux_vecs_count() const override;

static std::set<std::vector<element::Type>> get_supported_precisions(const std::shared_ptr<ov::Node>& node = nullptr);

private:
void emit_impl(const std::vector<size_t> &in_vec_idxs, const
std::vector<size_t> &out_vec_idxs) const override;
template <dnnl::impl::cpu::aarch64::cpu_isa_t isa>
void emit_isa(const std::vector<size_t> &in_vec_idxs, const std::vector<size_t> &out_vec_idxs) const;
};


class jit_sigmoid_emitter : public jit_emitter {
public:
jit_sigmoid_emitter(dnnl::impl::cpu::aarch64::jit_generator* host,
Expand Down
1 change: 1 addition & 0 deletions src/plugins/intel_cpu/src/nodes/executors/aarch64/jit_eltwise.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,7 @@ bool JitEltwiseExecutor::isSupported(
Algorithm::EltwisePrelu,
Algorithm::EltwiseRelu,
Algorithm::EltwiseSelect,
Algorithm::EltwiseSoftPlus,
Algorithm::EltwiseSigmoid,
Algorithm::EltwiseSubtract,
Algorithm::EltwiseSwish,
Expand Down
2 changes: 2 additions & 0 deletions src/plugins/intel_cpu/src/nodes/kernels/aarch64/jit_uni_eltwise_generic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -634,6 +634,7 @@ std::shared_ptr<jit_emitter> jit_uni_eltwise_generic<isa>::create_eltwise_emitte
OV_CASE(Algorithm::EltwisePrelu, ov::intel_cpu::aarch64::jit_prelu_emitter),
OV_CASE(Algorithm::EltwiseRelu, ov::intel_cpu::aarch64::jit_relu_emitter),
OV_CASE(Algorithm::EltwiseSelect, ov::intel_cpu::aarch64::jit_select_emitter),
OV_CASE(Algorithms::EltwiseSoftPlus, ov::intel_cpu::aarch64::jit_soft_plus_emitter),
OV_CASE(Algorithm::EltwiseSigmoid, ov::intel_cpu::aarch64::jit_sigmoid_emitter),
OV_CASE(Algorithm::EltwiseSubtract, ov::intel_cpu::aarch64::jit_subtract_emitter),
OV_CASE(Algorithm::EltwiseSwish, ov::intel_cpu::aarch64::jit_swish_emitter),
Expand Down Expand Up @@ -797,6 +798,7 @@ std::set<std::vector<element::Type>> eltwise_precision_helper::get_supported_pre
OV_CASE(Algorithm::EltwisePrelu, jit_prelu_emitter),
OV_CASE(Algorithm::EltwisePowerStatic, jit_power_static_emitter),
OV_CASE(Algorithm::EltwiseSelect, jit_select_emitter),
OV_CASE(Algorithms::EltwiseSoftPlus, jit_soft_plus_emitter),
OV_CASE(Algorithm::EltwiseSigmoid, jit_sigmoid_emitter),
OV_CASE(Algorithm::EltwiseSubtract, jit_subtract_emitter),
OV_CASE(Algorithm::EltwiseSwish, jit_swish_emitter),
Expand Down
1 change: 1 addition & 0 deletions src/plugins/intel_cpu/tests/functional/custom/single_layer_tests/classes/activation.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -157,6 +157,7 @@ std::string ActivationLayerCPUTest::getPrimitiveType(const utils::ActivationType
(activation_type == utils::ActivationTypes::Exp) ||
(activation_type == utils::ActivationTypes::HSwish) ||
(activation_type == utils::ActivationTypes::Relu) ||
(activation_type == utils::ActivationTypes::Softplus) ||
(activation_type == utils::ActivationTypes::Sigmoid) ||
(activation_type == utils::ActivationTypes::Swish) ||
(activation_type == utils::ActivationTypes::Tanh))) {
Expand Down
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