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DFF.v

@@ -0,0 +1,10 @@
+module DFF(clk, in, out);
+	parameter n=8; //bits held
+	input clk;
+	input [n-1:0] in;
+	output [n-1:0] out;
+	reg [n-1:0] out;
+
+	always@(posedge clk)
+		out = in;
+endmodule

FAdder.v

@@ -0,0 +1,10 @@
+//multi-bit adder
+module FAdder(first, second, carryIn, carryOut, sum);
+	parameter n=8;
+	input [n-1:0] first, second;
+	input carryIn;
+	output [n-1:0] sum;
+	output carryOut;
+
+	assign {carryOut, sum} = first + second + carryIn;
+endmodule

FSM.v

@@ -0,0 +1,132 @@
+// Finite State Machine Factorization
+// Defining states for
+`define SWIDTH 2
+`define S_off         2'b00
+`define S_ready       2'b01
+`define S_run         2'b10
+`define S_run_error   2'b11
+
+
+// define time intervals
+// load 4 for 5-cycle interval 4 to 0.
+// load 3 for 4-cycle interval 3 to 0.
+//`define T_WIDTH 3
+//`define T_ON  3'd4
+//`define T_OFF 3'd3
+
+// defines for pulse counter
+// load with 3 for four pulses
+`define C_WIDTH 2
+`define C_COUNT 3
+
+//----------------------------------------------------------------------
+// Flash module
+//----------------------------------------------------------------------
+module Flash(clk, rst, in, out) ;
+  input clk, rst, in ; // in triggers start of flash sequence
+  output [1:0] out ;	       // out drives LED
+  reg [1:0] out ;                       // output
+  wire [`SWIDTH-1:0] state, next ; // current state
+  reg  [`SWIDTH-1:0] next1  ;      // next state without reset
+  reg  tload, tsel ;               // timer inputs
+  wire done ;                      // timer output
+
+  // instantiate state register
+  DFF #(`SWIDTH) state_reg(clk, next, state) ;
+
+  // instantiate timer
+  // Timer1 timer(clk, rst, tload, tsel, done) ;
+
+  always @(*) begin
+    case(state)
+      `S_off:   {error, next1} =
+                {outOverflow, on ? `S_ready : `S_off } ;
+      `S_ready: {error, next1} =
+                {outOverflow, load ? `S_run : `S_ready } ;
+      `S_run:   {error, next1} =
+                {outOverflow, outOverflow ? `S_run_error : `S_run } ;
+      `S_run_error:   {error, next1} =
+                      {outOverflow, `S_ready } ;
+      default:  {error, next1} =
+                {outOverflow, on ? `S_ready : `S_off } ;
+    endcase
+  end
+
+  assign next = rst ? `S_ready : next1 ;
+endmodule
+
+//------------------------------------------
+module DFF(clk,in,out);
+// DFF module
+//---------------------------------------------
+  parameter n=1;//width
+  input clk;
+  input [n-1:0] in;
+  output [n-1:0] out;
+  reg [n-1:0] out;
+
+  always @(posedge clk)
+  out = in;
+ endmodule
+//-------------------------------------------------------------
+
+//----------------------------------------------------------------------
+// Timer1 - count down timer
+//   tload - loads timer
+//   tsel  - selects between `T_ON and `T_OFF for time interval in cycle
+//           when tload is asserted
+//   done - signals when selected time interval has completed.
+//----------------------------------------------------------------------
+module Timer1(clk, rst, tload, tsel, done) ;
+  parameter n=`T_WIDTH ;
+  input clk, rst, tload, tsel ;
+  output done ;
+  wire [n-1:0] count ;
+  reg  [n-1:0] next_count ;
+
+  // state register
+  DFF #(n) state(clk, next_count, count) ;
+
+  // signal done
+  assign done = ~(|count) ;
+
+  // next count logic
+  always@(*) begin
+    casex({rst, tload, tsel, done})
+      4'b1xxx: next_count = `T_WIDTH'b0 ;
+      4'b011x: next_count = `T_ON ;
+      4'b010x: next_count = `T_OFF ;
+      4'b00x0: next_count = count - 1'b1 ;
+      4'b00x1: next_count = count ;
+      default: next_count = count ;
+    endcase
+  end
+endmodule
+//-------------------------------------------------------------
+module TestFlash ;
+  reg clk, rst, in ;
+  wire out ;
+
+  Flash f(clk, rst, in, out) ;
+
+  // clock and display
+  initial
+    forever
+      begin
+        #5 clk = 0 ;
+        $display("%b %b", in, out) ;
+        #5 clk = 1 ;
+      end
+
+  // inputs
+  initial begin
+    #5 rst = 1 ; in = 0 ;
+    #10 rst = 0 ;
+    #10 in = 1 ;
+    #10 in = 0 ;
+    #320 in = 1 ;
+    #10 in = 0 ;
+    #320 $stop ;
+  end
+endmodule
+//----------------------------------------------------------

add.v

@@ -0,0 +1,7 @@
+module add(first, second, carryOut, sum);
+	input[7:0] first, second;
+	output [7:0] sum;
+	output carryOut;
+
+	assign{carryOut, sum} = first+second;
+endmodule

logicGate.v

@@ -0,0 +1,35 @@
+//write a testbench to test each
+
+module ANDgate (a, b, y);
+	input [7:0] a, b;
+	output [7:0] y;
+
+	assign y = a & b;
+
+endmodule
+/////////////////////////////////////////////////////////////////////
+
+module ORgate (a, b, y);
+	input [7:0] a, b;
+	output [7:0] y;
+
+	assign y = a | b;
+endmodule
+
+//////////////////////////////////////////////////////////////////////
+
+module NOTgate (a, y);
+	input[7:0] a;
+	output [7:0] y;
+
+	assign y = ~a;
+endmodule
+
+//////////////////////////////////////////////////////////////////////
+
+module XORgate (a, b, y);
+	input [7:0] a, b;
+	output [7:0] y;
+
+	assign y = a ^ b;
+endmodule

main.v

@@ -0,0 +1,52 @@
+module main(clk, in_selector, num1, num2, out_selector)	//4 different inputs: 2 different numbers, 
+													//and 1 input selecter bit for the input mux, 1 output selecter bit for the output mux
+
+	input [2:0] in_selector; //persist, load, reset
+	input reg[7:0] num1;
+	input reg[7:0] num2;
+	input [6:0] out_selector; //and, or, not, xor, add, sub, mult
+	input clk;
+	wire [7:0] outputVal;
+	wire [7:0] outM1;
+	wire [7:0] outM2;
+	wire [7:0] outDFF1;
+	wire [7:0] outDFF2;
+	wire [7:0] outAnd;
+	wire [7:0] outOr;
+	wire [7:0] outNot;
+	wire [7:0] outXor;
+	wire [7:0] outMult;
+	wire outOverflow;
+	wire carryOutToNowhere;
+	wire [7:0] sum;
+	wire [7:0] diff;
+
+	output outputVal;
+
+	MuxFF #(8) ff_1(outputVal, num1, 8'b00000000, in_selector, outM1);
+	MuxFF #(8) ff_2(num2, num2, 8'b00000000, in_selector, outM2);
+
+	DFF #(8) dff_1(clk, outM1, outDFF1);
+	DFF #(8) dff_2(clk, outM2, outDFF2);
+
+	ANDgate andGate(outDFF1, outDFF2, outAnd);
+	ORgate andGate(outDFF1, outDFF2, outOr);
+	NOTgate andGate(outDFF1, outNot);
+	XORgate andGate(outDFF1, outDFF2, outXor);
+
+	Mult multed(outDFF1, outDFF2, outOverflow, outMult);
+	add myAdd(outDFF1, outDFF2, carryOutToNowhere, sum);
+	sub mySub(outDFF1, outDFF2, diff);
+
+	MuxOut(outAnd, outOr, outXor, outNot, add, sub, outMult, out_selector, outputVal);
+
+
+
+
+endmodule
+
+
+
+
+
+

main_tb.v

@@ -0,0 +1,13 @@
+module TestBench;
+
+	reg [2:0]in_sel;
+	reg [5:0] out_sel;
+	reg [7:0] num1, num2;
+	wire [7:0] out;
+
+	main myMain(in_sel, num1, num2, out_sel);
+
+	initial begin
+		in_sel = 3'b010; num1 = 8'b01010111; num2 = 8'b00011010;
+			#0
+		#10 

mult.v

@@ -0,0 +1,31 @@
+module Mult(first, second, errorWire, outWire);
+	input [7:0] first, second;
+	output [7:0] outWire;
+	output errorWire;
+
+	//partial products
+	wire [7:0] pp0 = first & {8{second[0]}}; //x1
+	wire [7:0] pp1 = first & {8{second[1]}}; //x2
+	wire [7:0] pp2 = first & {8{second[2]}}; //x4
+	wire [7:0] pp3 = first & {8{second[3]}}; //x8
+	wire [7:0] pp4 = first & {8{second[4]}}; //x16
+	wire [7:0] pp5 = first & {8{second[5]}}; //x32
+	wire [7:0] pp6 = first & {8{second[6]}}; //x64
+	wire [7:0] pp7 = first & {8{second[7]}}; //x128
+
+	//sum up partial products
+	wire addOut1, addOut2, addOut3, addOut4, addOut5, addOut6, addOut7;
+	wire [7:0] sum1, sum2, sum3, sum4, sum5, sum6, sum7;
+	FAdder #(8) fa1(pp1, {1'b0,pp0[7:1]}, 1'b0, addOut1, sum1);
+	FAdder #(8) fa2(pp2, {addOut1,sum1[7:1]}, 1'b0, addOut2, sum2);
+	FAdder #(8) fa3(pp3, {addOut2,sum2[7:1]}, 1'b0, addOut3, sum3);
+	FAdder #(8) fa2(pp4, {addOut3,sum3[7:1]}, 1'b0, addOut4, sum4);
+	FAdder #(8) fa2(pp5, {addOut4,sum4[7:1]}, 1'b0, addOut5, sum5);
+	FAdder #(8) fa2(pp6, {addOut5,sum5[7:1]}, 1'b0, addOut6, sum6);
+	FAdder #(8) fa2(pp7, {addOut6,sum6[7:1]}, 1'b0, addOut7, sum7);
+
+	//result
+	wire[7:0] outWire = {sum7[0], sum6[0], sum5[0], sum4[0], sum3[0], sum2[0],sum1[0], pp0[0]};
+	wire errorWire = {addOut7, sum7[7:1]} ? 1:0;
+	//wire [15:0] outWire = {addOut7, sum7, sum6[0], sum5[0], sum4[0], sum3[0], sum2[0],sum1[0],pp0[0]};
+endmodule

muxFF.v

@@ -0,0 +1,9 @@
+module MuxFF(keep_val, load, clear, sel, outWire);
+	parameter k= 3; //# of inputs, can override in instantiation
+	input [k-1:0] keep_val, load, clear; //inputs
+	input [2:0] sel; //1-hot select
+	output [k-1:0] outWire;
+	wire [k-1:0] outWire = ({k{s[0]}} & keep_val) |
+													({k{s[1]}} & load) |
+													({k{s[2]}} & clear);
+endmodule

muxOut.v

@@ -0,0 +1,14 @@
+module MuxOut(logAnd, logOr, logXor, logNot, addSub, mult, sel, outWire);
+	parameter k =7; //k = # inputs. can override in instantiation
+	//override when called like MuxOut #(k_override_num) Instance_of_MuxOut(logAdd_thing, logOr_thing,...);
+	input [k-1:0] logAnd, logOr, logXor, logNot, addSub, mult; //inputs
+	input [5:0] sel; //1-hot select
+	output[k-1:0] b;
+	wire [k-1:0] b = ({k{s[0]}} & logAnd) |
+										({k{s[1]}} & logOr) |
+										({k{s[2]}} & logXor) |
+										({k{s[3]}} & logNot) |
+										({k{s[4]}} & addSub) |
+										({k{s[5]}} & mult);
+endmodule
+

sub.v

@@ -0,0 +1,6 @@
+module sub(first, second, diff);
+	input[7:0] first, second;
+	output [7:0] diff;
+
+	assign{diff} = first-second;
+endmodule