Add hovering!

multiply_add.sus

@@ -436,7 +436,15 @@ module undeteriminable_input_latency : int a, int b -> int x, int y {
     y = t;
 }
 
-module manually_specified_input_latency : int a'0, int b'1 -> int x, int y {
+module determinable_input_latency : int a, int b -> int x, int y {
+	reg int a_d = a;
+    reg int t = a_d + b;
+    reg reg int a_ddd = a;
+    x = t + a_ddd;
+    y = t;
+}
+
+module specified_input_latency : int a'0, int b'1 -> int x, int y {
 	reg int a_d = a;
     reg int t = a_d + b;
     reg reg reg int a_ddd = a;

src/ast.rs

@@ -49,7 +49,7 @@ impl Span {
         Span(0, tokens.token_types.len())
     }
     pub fn contains_token(&self, token_idx : usize) -> bool {
-        self.0 >= token_idx && self.1 <= token_idx
+        token_idx >= self.0 && token_idx <= self.1
     }
     // Not really a useful quantity. Should only be used comparatively, find which is the nested-most span
     pub fn size(&self) -> usize {

src/instantiation/mod.rs

@@ -680,4 +680,13 @@ impl InstantiationList {
     pub fn clear_instances(&mut self) {
         self.cache.borrow_mut().clear()
     }
+
+    pub fn for_each_instance<F : FnMut(&InstantiatedModule)>(&self, mut f : F) {
+        let borrow = self.cache.borrow();
+        for v in borrow.iter() {
+            if let Some(vv) = &v.0 {
+                f(vv.as_ref())
+            }
+        }
+    }
 }

src/linker.rs

@@ -1,6 +1,6 @@
 use std::{collections::{HashMap, HashSet}, rc::Rc, cell::RefCell};
 
-use crate::{arena_alloc::{ArenaAllocator, UUID, UUIDMarker}, ast::{Module, LinkInfo, Span}, errors::{ErrorCollector, error_info}, flattening::{ConnectionWrite, FlatID, FlattenedModule, Instruction, WireInstance}, instantiation::InstantiatedModule, parser::{FullParseResult, TokenTreeNode}, tokenizer::TokenizeResult, typing::{WrittenType, Type}, util::{const_str_position, const_str_position_in_tuples}, value::Value};
+use crate::{arena_alloc::{ArenaAllocator, UUIDMarker, UUID}, ast::{LinkInfo, Module, Span}, errors::{error_info, ErrorCollector}, flattening::{ConnectionWrite, FlatID, FlattenedModule, Instruction, WireInstance, WireSource}, instantiation::InstantiatedModule, parser::{FullParseResult, TokenTreeNode}, tokenizer::TokenizeResult, typing::{Type, WrittenType}, util::{const_str_position, const_str_position_in_tuples}, value::Value};
 
 #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
 pub struct ModuleUUIDMarker;
@@ -219,6 +219,13 @@ impl Linker {
             }
         }
     }
+    pub fn get_full_name(&self, global : NameElem) -> String {
+        match global {
+            NameElem::Module(id) => self.modules[id].link_info.get_full_name(),
+            NameElem::Type(id) => self.types[id].get_full_name(),
+            NameElem::Constant(id) => self.constants[id].get_full_name(),
+        }
+    }
     fn get_linking_error_location(&self, global : NameElem) -> LinkingErrorLocation {
         match global {
             NameElem::Module(id) => {
@@ -381,7 +388,8 @@ impl Linker {
                 NameElem::Module(md_id) => {
                     let md = &self.modules[md_id];
                     if md.link_info.span.contains_token(token_idx) {
-                        for (_id, inst) in &md.flattened.instructions {
+                        location_builder.update(md.link_info.name_span, LocationInfo::Global(NameElem::Module(md_id)));
+                        for (id, inst) in &md.flattened.instructions {
                             match inst {
                                 Instruction::SubModule(sm) => {
                                     location_builder.update(sm.module_name_span, LocationInfo::Global(NameElem::Module(sm.module_uuid)));
@@ -392,10 +400,15 @@ impl Linker {
                                     }
                                 }
                                 Instruction::Wire(wire) => {
-                                    location_builder.update(wire.span, LocationInfo::Wire(md, wire));
+                                    let loc_info = if let WireSource::WireRead(decl_id) = &wire.source {
+                                        LocationInfo::WireRef(md, *decl_id)
+                                    } else {
+                                        LocationInfo::Temporary(md, id, wire)
+                                    };
+                                    location_builder.update(wire.span, loc_info);
                                 }
                                 Instruction::Write(write) => {
-                                    location_builder.update(Span::new_single_token(write.to.span.0), LocationInfo::WriteWire(md, &write.to));
+                                    location_builder.update(Span::new_single_token(write.to.span.0), LocationInfo::WireRef(md, write.to.root));
                                 }
                                 Instruction::IfStatement(_) | Instruction::ForStatement(_) => {}
                             };
@@ -419,9 +432,10 @@ impl Linker {
     }
 }
 
+#[derive(Clone, Copy, Debug)]
 pub enum LocationInfo<'linker> {
-    WriteWire(&'linker Module, &'linker ConnectionWrite),
-    Wire(&'linker Module, &'linker WireInstance),
+    WireRef(&'linker Module, FlatID),
+    Temporary(&'linker Module, FlatID, &'linker WireInstance),
     Type(&'linker WrittenType),
     Global(NameElem)
 }

src/main.rs

@@ -80,7 +80,7 @@ fn main() -> Result<(), Box<dyn Error + Sync + Send>> {
     let _executable_path = args.next();
 
     let mut file_paths : Vec<PathBuf> = Vec::new();
-    let mut is_lsp = false;
+    let mut is_lsp = None;
     let mut codegen = None;
     let mut codegen_all = false;
     let mut test_sus_sitter = false;
@@ -91,7 +91,10 @@ fn main() -> Result<(), Box<dyn Error + Sync + Send>> {
     while let Some(arg) = args.next() {
         match arg.as_str() {
             "--lsp" => {
-                is_lsp = true;
+                is_lsp = Some(false);
+            }
+            "--lsp-debug" => {
+                is_lsp = Some(true);
             }
             "--codegen" => {
                 codegen = Some(args.next().expect("Expected a module name after --codegen"));
@@ -112,8 +115,8 @@ fn main() -> Result<(), Box<dyn Error + Sync + Send>> {
     }
 
     #[cfg(feature = "lsp")]
-    if is_lsp {
-        return dev_aid::lsp::lsp_main(25000);
+    if let Some(debug) = is_lsp {
+        return dev_aid::lsp::lsp_main(25000, debug);
     }
     if file_paths.len() == 0 {
         // Quick debugging

src/tokenizer.rs

@@ -210,6 +210,16 @@ pub struct CharLine {
     pub line : usize,
     pub character : usize
 }
+impl PartialOrd for CharLine {
+    fn partial_cmp(&self, other: &Self) -> Option<std::cmp::Ordering> {
+        Some(self.cmp(other))
+    }
+}
+impl Ord for CharLine {
+    fn cmp(&self, other: &Self) -> std::cmp::Ordering {
+        self.line.cmp(&other.line).then(self.character.cmp(&other.character))
+    }
+}
 
 pub struct TokenizeResult {
     pub token_types : Vec<TokenTypeIdx>,
@@ -265,6 +275,15 @@ impl TokenizeResult {
     pub fn get_span_linechar_range(&self, span : Span) -> Range<CharLine> {
         self.token_boundaries_as_char_lines[span.0*2+1]..self.token_boundaries_as_char_lines[span.1*2+2]
     }
+
+    pub fn get_token_on_or_left_of(&self, char_line : CharLine) -> usize {
+        match self.token_boundaries_as_char_lines.binary_search(&char_line) {
+            Ok(idx) | Err(idx) => {
+                assert!(idx >= 1);
+                return (idx - 1) / 2;
+            }
+        }
+    }
 }
 
 pub fn tokenize<'txt>(file_text : &'txt str, errors : &ErrorCollector) -> TokenizeResult {

valid_syntax.sus

@@ -0,0 +1,228 @@
+
+
+
+module multiply_add : 
+	int a,
+	int b,
+	int c
+	-> int total {
+
+	reg int tmp = a * b;
+	total = tmp + c;
+}
+
+module fibonnaci : -> int num {
+	state int current = 1;
+	state int current_prev = 0;
+
+	num = current + current_prev;
+	current_prev = current;
+	current = num;
+}
+
+//timeline (v, true -> /) .. (v, false -> v)*
+module blur2 : 
+	int data,
+	bool first
+	-> int blurred {
+
+	state int prev;
+
+	if !first {
+		blurred = data + prev;
+	}
+	prev = data;
+
+	gen int a;
+
+	gen bool b = true;
+	gen bool bb = false;
+
+	if bb {
+		a = 5;
+	} else {
+		a = 3;
+	}
+}
+
+
+module Tree_Multiply : int[4] values -> int total {
+    int a = values[0] * values[1];
+	int b = values[2] * values[3];
+	total = a * b;
+}
+
+
+
+
+//timeline (X, false -> /)* .. (X, true -> T)
+module Accumulator : int term, bool done -> int total {
+    state int tot;
+	initial tot = 0;
+
+    int new_tot = tot + term;
+    if done {
+        total = new_tot;
+        tot = 0; // Must restore initial conditions
+    } else {
+        tot = new_tot;
+    }
+}
+
+
+//timeline (a, true -> /) | (a, false -> /) .. (a, false -> r)* .. (a, true -> r)
+module blur : int a, bool done -> int result {
+	state bool working;
+	initial working = false;
+	state int prev;
+
+	if working {
+		reg reg reg result = prev + a; // Add a pipeline stage for shits and giggles
+	}
+	prev = a;
+	working = !done;
+}
+
+
+
+//timeline (X -> X) .. (/ -> X) .. (/ -> X) .. (/ -> X)
+module Unpack4 : int[4] packed -> int out_stream {
+    state int st;
+	initial st = 0;
+    state int[3] stored_packed;
+
+    if st == 0 {
+        out_stream = packed[0];
+        stored_packed[0] = packed[1]; // Shorthand notation is possible here "stored_packed[0:2] = packed[1:3];"
+        stored_packed[1] = packed[2];
+        stored_packed[2] = packed[3];
+        st = 1;
+    } else if st == 1 {
+        out_stream = stored_packed[0];
+        st = 2;
+    } else if st == 2 {
+        out_stream = stored_packed[1];
+        st = 3;
+    } else if st == 3 {
+        out_stream = stored_packed[2];
+        st = 0; // Must restore initial conditions
+        //finish; // packet is hereby finished. 
+    }
+}
+
+module generative : int i -> int o, int o2 {
+	gen int x = 5;
+	gen int[x] ys;
+
+	//gen int[ys] zs;
+
+	gen int[3] ps;
+
+	gen int[x] a;
+
+	a[2] = 5;
+	a[1] = 2;
+	a[0] = 10;
+	gen int[3] xx = a;
+
+	gen bool test = true;
+
+	if test {
+
+	}
+
+	o = a[i];
+	o2 = a[a[0]];
+}
+
+module add_stuff_to_indices : int[10] values -> int[10] added_values {
+	for int i in 0..10 {
+		int sum = values[i] + i;
+		added_values[i] = sum;
+	}
+}
+
+
+//timeline (bs -> /, true) | (bs -> v, false)
+module first_bit_idx_6 : bool[6] bits -> int first, bool all_zeros {
+	if bits[0] {
+		first = 0;
+		all_zeros = false;
+	} else if bits[1] {
+		first = 1;
+		all_zeros = false;
+	} else if bits[2] {
+		first = 2;
+		all_zeros = false;
+	} else if bits[3] {
+		first = 3;
+		all_zeros = false;
+	} else if bits[4] {
+		first = 4;
+		all_zeros = false;
+	} else if bits[5] {
+		first = 5;
+		all_zeros = false;
+	} else {
+		all_zeros = true;
+	}
+
+	/*first int i in 0..6 where bits[i] {
+		first = i;
+		all_zeros = false;
+	} else {
+		all_zeros = true;
+	}*/
+
+}
+
+
+module disjoint_ports : int a, int b, int c -> int result {
+	reg result = a + b;
+	// don't touch c
+}
+
+module undeteriminable_input_latency : int a, int b -> int x, int y {
+	reg int a_d = a;
+    reg int t = a_d + b;
+    reg reg reg int a_ddd = a;
+    x = t + a_ddd;
+    y = t;
+}
+
+module determinable_input_latency : int a, int b -> int x, int y {
+	reg int a_d = a;
+    reg int t = a_d + b;
+    reg reg int a_ddd = a;
+    x = t + a_ddd;
+    y = t;
+}
+
+module specified_input_latency : int a'0, int b'1 -> int x, int y {
+	reg int a_d = a;
+    reg int t = a_d + b;
+    reg reg reg int a_ddd = a;
+    x = t + a_ddd;
+    y = t;
+}
+
+module bad_cycle : int a -> int r {
+	state int test;
+	initial test = 0;
+
+	reg int new_test = test + a;
+	test = new_test;
+
+	r = new_test;
+}
+
+module good_cycle : int a -> int r {
+	state int test;
+	initial test = 0;
+
+	int new_test = test + a;
+	test = new_test;
+
+	r = new_test;
+}
+