Moved connections to Instance List

pc2 · Dec 15, 2023 · 866a912 · 866a912
1 parent 8e5f52c
commit 866a912
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Showing 4 changed files with 27 additions and 26 deletions.
diff --git a/src/codegen_fallback.rs b/src/codegen_fallback.rs
@@ -42,7 +42,7 @@ pub fn value_to_str(value : &Value) -> String {
     }
 }
 
-pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule, linker : &Linker) -> Option<String> {
+pub fn gen_verilog_code(md : &Module, instance : &InstantiatedModule) -> Option<String> {
     let mut program_text : String = format!("module {}(\n\tinput clk, \n", md.link_info.name);
     for (port, real_port) in zip(&md.interface.interface_wires, &instance.interface) {
         if real_port.id == UUID::INVALID {return None;}

diff --git a/src/flattening.rs b/src/flattening.rs
@@ -49,6 +49,7 @@ pub enum Instantiation {
     BinaryOp{typ : Type, op : Operator, left : SpanFlatID, right : SpanFlatID},
     ArrayAccess{typ : Type, arr : SpanFlatID, arr_idx : SpanFlatID},
     Constant{typ : Type, value : Value},
+    Connection(Connection),
     Error
 }
 
@@ -61,6 +62,7 @@ impl Instantiation {
             Instantiation::BinaryOp{typ, op : _, left : _, right : _} => typ,
             Instantiation::ArrayAccess{typ, arr : _, arr_idx : _} => typ,
             Instantiation::Constant{typ, value : _} => typ,
+            Instantiation::Connection(_) => panic!("Calling get_type on Connection!"),
             Instantiation::Error => panic!("This was not properly resolved!")
         }
     }
@@ -79,6 +81,7 @@ impl Instantiation {
             Instantiation::BinaryOp { typ : _, op : _, left, right } => {f(left.0); f(right.0);}
             Instantiation::ArrayAccess { typ : _, arr, arr_idx } => {f(arr.0); f(arr_idx.0)}
             Instantiation::Constant { typ : _, value : _ } => {}
+            Instantiation::Connection(_) => panic!("Calling iter_sources on Connection!"),
             Instantiation::Error => {}
         }
     }
@@ -95,7 +98,6 @@ pub struct Connection {
 struct FlatteningContext<'l, 'm, 'fl> {
     decl_to_flat_map : FlatAlloc<FlatID, DeclIDMarker>,
     instantiations : &'fl ListAllocator<Instantiation, FlatIDMarker>,
-    connections : &'fl BlockVec<Connection>,
     errors : &'fl ErrorCollector,
 
     linker : &'l Linker,
@@ -137,7 +139,7 @@ impl<'l, 'm, 'fl> FlatteningContext<'l, 'm, 'fl> {
 
         self.typecheck(connection.from, &expected_type, "connection")?;
 
-        self.connections.alloc(connection);
+        self.instantiations.alloc(Instantiation::Connection(connection));
 
         Some(())
     }
@@ -462,7 +464,6 @@ impl FlattenedModule {
         let mut context = FlatteningContext{
             decl_to_flat_map: module.declarations.iter().map(|_| UUID::INVALID).collect(),
             instantiations: &flat_mod.instantiations,
-            connections: &flat_mod.connections,
             errors: &flat_mod.errors,
             linker,
             module,
@@ -499,7 +500,6 @@ impl FlattenedModule {
         let mut context = FlatteningContext {
             decl_to_flat_map : decl_to_flat_map,
             instantiations : &self.instantiations,
-            connections : &self.connections,
             errors : &self.errors,
             module,
             linker,

diff --git a/src/instantiation/mod.rs b/src/instantiation/mod.rs
@@ -203,7 +203,7 @@ impl<'fl, 'l> InstantiationContext<'fl, 'l> {
                         self.instance_map[port.id].extract_wire()
                     }).collect();
                     SubModuleOrWire::SubModule(self.submodules.alloc(SubModule { original_flat: original_wire, instance, wires : interface_real_wires, name : name.clone()}))
-                },
+                }
                 Instantiation::PlainWire{read_only, identifier_type, typ, decl_id} => {
                     let source = if *read_only {
                         RealWireDataSource::ReadOnly
@@ -213,37 +213,38 @@ impl<'fl, 'l> InstantiationContext<'fl, 'l> {
                         RealWireDataSource::Multiplexer {is_state, sources : Vec::new()}
                     };
                     self.add_wire(decl_id.map(|id| self.module.declarations[id].name.clone()), typ, original_wire, source)
-                },
+                }
                 Instantiation::UnaryOp{typ, op, right} => {
                     self.add_wire(None, typ, original_wire, RealWireDataSource::UnaryOp{op: *op, right: self.instance_map[right.0].extract_wire() })
-                },
+                }
                 Instantiation::BinaryOp{typ, op, left, right} => {
                     self.add_wire(None, typ, original_wire, RealWireDataSource::BinaryOp{op: *op, left: self.instance_map[left.0].extract_wire(), right: self.instance_map[right.0].extract_wire() })
-                },
+                }
                 Instantiation::ArrayAccess{typ, arr, arr_idx} => {
                     self.add_wire(None, typ, original_wire, RealWireDataSource::ArrayAccess{arr: self.instance_map[arr.0].extract_wire(), arr_idx: self.instance_map[arr_idx.0].extract_wire() })
-                },
+                }
                 Instantiation::Constant{typ, value} => {
                     self.add_wire(None, typ, original_wire, RealWireDataSource::Constant{value : value.clone() })
-                },
+                }
+                Instantiation::Connection(conn) => {
+                    let condition = if conn.condition != UUID::INVALID {
+                        self.instance_map[conn.condition].extract_wire()
+                    } else {
+                        UUID::INVALID
+                    };
+                    let conn_from = ConnectFrom {
+                        num_regs: conn.num_regs,
+                        from: self.instance_map[conn.from.0].extract_wire(), // TODO Span?
+                        condition,
+                    };
+
+                    self.process_connection(&conn.to, conn_from);
+                    continue;
+                }
                 Instantiation::Error => {unreachable!()},
             };
             self.instance_map[original_wire] = instance_to_add;
         }
-        for conn in &self.module.flattened.connections {
-            let condition = if conn.condition != UUID::INVALID {
-                self.instance_map[conn.condition].extract_wire()
-            } else {
-                UUID::INVALID
-            };
-            let conn_from = ConnectFrom {
-                num_regs: conn.num_regs,
-                from: self.instance_map[conn.from.0].extract_wire(), // TODO Span?
-                condition,
-            };
-
-            self.process_connection(&conn.to, conn_from);
-        }
     }
 
     fn make_interface(&self) -> Vec<InstantiatedInterfacePort> {

diff --git a/src/main.rs b/src/main.rs
@@ -34,7 +34,7 @@ fn codegen_to_file(linker : &Linker, id : NamedUUID, md : &Module) {
     let module_name = md.link_info.name.deref();
     println!("Generating Verilog for {module_name}:");
     // gen_ctx.to_circt();
-    let Some(code) = gen_verilog_code(md, &inst, &linker) else {println!("Error"); return;};
+    let Some(code) = gen_verilog_code(md, &inst) else {println!("Error"); return;};
 
     let mut out_file = File::create(format!("verilog_output/{module_name}.v")).unwrap();
     write!(out_file, "{}", code).unwrap()