Added missing compiler runtime routines.

.gitignore

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+
+.DS_Store

AgExamples/hello_world/.gitignore

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+obj/
+bin/
+src/gfx/*.c
+src/gfx/*.h
+src/gfx/*.8xv
+.DS_Store
+convimg.out

Zilog/fpadd.asm

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+;--------------------------------------------------------------
+;
+;			Code Generation Helper
+;		    For the Zilog eZ80 C Compiler
+;	        Copyright 1992-2008 Zilog, Inc. 
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+;	  	IEEE Single precision add
+;
+; INPUTS:	AuBC		OP1.
+;		EuHL		OP2.
+;
+; OUTPUTS:	AuBC		Sum.
+;
+; Returns the result of adding the absolute values of the single-precision
+; floating-point values OP1 and OP2.  If Sign of result is 1, the sum is
+; negated before being returned.
+;
+;--------------------------------------------------------------
+
+	segment	CODE
+	.assume adl=1
+	.ref	__fpupop1, __fpupop2, __fppack
+	.def    __fadd
+__fadd:
+	push	hl
+	push	de
+	call	__fpupop1	;unpack operand 1
+	rr	d		;carry = sign
+	push	af		;save sign
+	call	__fpupop2	;unpack operand 2
+	pop	af
+	rl	d		;D has both sign bits (00000021)
+	rrc	d		;swap sign bit (0000021 -> 10000002)
+	cp	a,e		;exp op1 < exp op2 ?
+	jr	c,less		;- yes, skip
+
+	rlc	d		;swap sign bit (1000002 -> 00000021)
+	push	hl
+	push	bc
+	ld	b,a
+	ld	a,e
+	ld	e,b
+	pop	hl
+	pop	bc		;swap operands
+less:
+	sub	a,e
+	jr	z,noshift
+
+	cp	a,-24		;too much shift?
+	ccf			;(reset carry if jump)
+	jr	nc,noadd	;- yes, skip add
+
+	push	ix
+	push	de
+	push	bc
+	ld	ix,0
+	add	ix,sp
+	ld	d,(ix+2)
+loop1:
+	srl	d		;shift uBC right
+	rr	b
+	rr	c
+	inc	a
+	jr	nz,loop1
+
+	ld	(ix),bc
+	ld	(ix+2),d
+	pop	bc
+	pop	de
+	pop	ix
+noshift:
+	ld	a,d
+	and	a,a		;clear carry, set parity
+	jp	pe,doadd	;same sign, add
+
+	sbc	hl,bc
+	sbc	a,a
+	jr	common
+doadd:
+	add	hl,bc
+noadd:
+	ld	a,0
+	adc	a,a
+common:
+	push	hl
+	pop	bc
+	call	__fppack				
+	pop	de
+	pop	hl
+	ret
+

Zilog/fpcmp.asm

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+;--------------------------------------------------------------
+;
+;		Code Generation Helper
+;		For the Zilog eZ80 C Compiler
+;	        Copyright 1992-2008 Zilog, Inc. 
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+;	  	IEEE Single precision compare.
+;
+; INPUTS:
+;
+;	Operand1: 
+;		  EuHL : 32 bit IEEE format
+;
+;	Operand2: 
+;		  AuBC : 32 bit IEEE format
+;
+;
+; OUTPUTS:	FLAGS based on Op1 - Op2
+;
+;--------------------------------------------------------------
+	segment	CODE
+	.assume adl=1
+	.def	__fcmp
+	.ref	__lcmps
+
+__fcmp:
+	call	__lcmps
+	jr	z,exit1		; sign doesn't matter if equal
+
+	push	bc
+	push	af
+	pop	bc		; C = flags
+	ld	a,b
+	and	a,e
+	ld	a,c		; A = flags
+	jp	p,skip1		; not both negative
+
+	xor	a,80h		; invert sign bit
+skip1:
+	bit	2,a		; overflow bit set ?
+	jr	z,skip2		; - no, skip
+
+	xor	a,80h		; invert sign bit
+skip2:
+	ld	c,a
+	push	bc
+	pop	af
+	pop	bc
+exit1:
+	ret
+

Zilog/fpdiv.asm

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+;--------------------------------------------------------------
+;
+;	        Code Generation Helper
+;		For the Zilog eZ80 C Compiler
+;	        Copyright 1992-2008 Zilog, Inc. 
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+;	  	IEEE Single precision division
+;
+; INPUTS:
+;	Operand1: 
+;		  AuBC : 32 bit IEEE format
+;
+;	Operand2: 
+;		  EuHL : 32 bit IEEE format divisor
+;
+; OUTPUTS:
+;	Result:   AuBC : 32 bit IEEE Quotient.
+; Registers Used:
+;	flags
+;
+;--------------------------------------------------------------
+
+	segment	code
+
+	.assume adl=1
+	.ref	__fpupop1, __fpupop2, __fppack
+        .def    __fdiv
+
+__fdiv:
+	push	ix
+	push	iy
+	push	hl
+	push	de
+	call	__fpupop1	;unpack dividend
+	jr	z,exit3		;skip if zero to avoid loop
+
+	push	bc		;save dividend
+	ld	c,a		;save exponent
+	ld	a,d		;save sign
+	call	__fpupop2	;unpack divisor
+	push	hl		;save divisor
+	push	af		;save zero indication
+	xor	a,d		;compute result sign
+	ld	b,0
+	ld	d,0
+	ld	hl,7FH+24-1
+	add	hl,bc
+	sbc	hl,de		;compute result exponent
+	push	hl
+	pop	ix
+	ld	d,a		;save result sign
+	pop	af
+	pop	bc		;restore divisor
+	pop	hl		;restore dividend
+	jr	z,oflow		;skip if divisor zero
+
+	ld	iy,0
+	or	a		;clear carry
+loop1:
+	rla			;save HL shift overflow
+	add	iy,iy		;shift quotient left
+	jr	c,exit1		;exit loop when IY overflow
+
+	sbc	hl,bc
+	jr	nc,over
+
+	sra	a		;restore HL shift overflow
+	jr	c,over
+
+	add	hl,bc		;restore dividend
+	jr	under
+over:
+	inc	iy		;update quotient
+under:
+	dec	ix		;update exponent
+	add	hl,hl		;shift dividend left, including carry
+	jr	loop1
+exit1:
+	ld	e,0
+	sra	a		;restore carry
+	jr	c,round		;round if HL shift overflow
+
+	or	a		;clear carry
+	sbc	hl,bc		;round ?
+	jr	c,skip1		;- no, skip
+round:
+	ld	bc,1
+	add	iy,bc		;round
+	rl	e		;save any overflow
+skip1:
+	inc	e		;EuIY = quotient
+	ld	a,ixh
+	or	a,a		;high-order exponent zero?
+	jr	z,skip2		;- yes, skip
+
+	jp	m,uflow		;skip if underflow
+oflow:
+	scf			;set carry for overflow
+uflow:
+	sbc	hl,hl		;0 for uflow, -1 for oflow
+	ld	e,h		;ditto
+	ld	a,0
+	push	hl
+	jr	exit2
+skip2:
+	ld	a,e		;AuIY = quotient
+	ld	e,ixl		;set exponent
+	push	iy
+exit2:
+	pop	bc		;AuBC = quotient
+exit3:
+	call	__fppack
+	pop	de
+	pop	hl
+	pop	iy
+	pop	ix
+	ret
+

Zilog/fpftol.asm

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+;--------------------------------------------------------------
+;
+;	        Code Generation Helper
+;		For the Zilog eZ80 C Compiler
+;	        Copyright 1992-2008 Zilog, Inc. 
+;
+;--------------------------------------------------------------
+;--------------------------------------------------------------
+;
+;	  	IEEE Single precision to long.
+;
+; INPUTS:	abc:	32-bit	IEEE Single precision.
+;
+; OUTPUTS:	abc:	32-bit	signed long.
+;
+;--------------------------------------------------------------
+OP1EXP	EQU	0
+OP1MAN	EQU 1
+LOCALIM	EQU 10
+	segment	CODE
+	.assume adl=1
+	
+	.ref	__fpupop1, __lshrs, __lshl
+        .def    __ftol
+
+__ftol:
+	push	ix
+	ld	ix,0
+	add	ix,sp
+	push	iy
+	lea	iy,ix-LOCALIM
+	ld	sp,iy
+	push	de
+	push	hl
+	ld	de,0
+	ld	(iy+OP1MAN),d
+	ld	(iy+OP1MAN+4),d
+	ld	(iy+OP1MAN+1),de
+	call	__fpupop1
+	jr	z,exit 
+	cp	a,7FH
+	jp	m,retz		; fp value less than 1
+		
+	sub	a,7EH
+	ld	(iy+OP1EXP),a
+	cp	a,32		; fp value greater than 2**32?
+	jp	p,retmax	; too big for an int
+	xor	a,a
+	bit	0,d
+	jr	z,shftman	; positive sign, shift mantissa
+	;;
+	;; Mark as negative
+	;;
+	ld	(iy+OP1MAN+4),1
+shftman:
+	ld	(iy+OP1MAN),bc
+	ld	(iy+OP1MAN+3),a
+	ld	a,(iy+OP1EXP)
+	cp	a,24		; Exponent=24?
+	ld	a,(iy+OP1MAN+3)
+	jr	z,exit		; done
+	jp	p,shiftl	; must shift left
+	;;
+	;; integer smaller than 24 bits shift right
+	;;
+	ld	a,24
+	sub	a,(iy+OP1EXP)
+	ld	l,a
+	ld	a,(iy+OP1MAN+3)
+	call	__lshrs
+	jr	sgntest
+
+shiftl:
+	ld	a,(iy+OP1EXP)
+	sub	a,24
+	ld	l,a
+	ld	a,(iy+OP1MAN+3)
+	call	__lshl
+	jr	sgntest
+
+retz:
+	xor	a,a
+	ld	bc,0
+	jr	exit
+sgntest:	
+	bit	0,(iy+OP1MAN+4)
+	jr	z,exit
+	ld	hl,0
+	ld	e,a
+	xor	a,a
+	sbc	hl,bc
+	sbc	a,e
+	ld	bc,hl
+	jr	exit
+
+retmax:
+	ld	bc,FFFFFFH
+	ld	a,FFH
+	bit	0,d
+	jr	nz,exit
+	ld	a,7FH
+
+exit:		
+	pop	hl
+	pop	de
+	ld	iy,(ix-3)
+	ld	sp,ix
+	pop	ix
+	ret
+	end