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Acpi fixes #472

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Acpi fixes #472

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5006c70
src/northbridge/amd/pi/00730F01/acpi/northbridge.asl: remove obsolete…
miczyg1 Jun 7, 2021
c49a28c
src/southbridge/amd/pi/hudson/acpi: remove non-existent USB hubs
miczyg1 Jun 7, 2021
48ab913
src/mainboard/pcengines/apu2/mainboard.c: clear ACPI events
miczyg1 Jun 7, 2021
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43 changes: 11 additions & 32 deletions src/mainboard/pcengines/apu2/acpi/gpe.asl
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Original file line number Diff line number Diff line change
Expand Up @@ -2,50 +2,29 @@

Scope(\_GPE) { /* Start Scope GPE */

/* General event 3 */
Method(_L03) {
/* DBGO("\\_GPE\\_L00\n") */
}

/* Legacy PM event */
Method(_L08) {
/* DBGO("\\_GPE\\_L08\n") */
}

/* Temp warning (TWarn) event */
Method(_L09) {
/* DBGO("\\_GPE\\_L09\n") */
/* Notify (\_TZ.TZ00, 0x80) */
}

/* USB controller PME# */
Method(_L0B) {
/* DBGO("\\_GPE\\_L0B\n") */
Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.EHC1, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.EHC2, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.EHC3, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* ExtEvent0 SCI event */
Method(_L10) {
/* DBGO("\\_GPE\\_L10\n") */
}

/* ExtEvent1 SCI event */
Method(_L11) {
/* DBGO("\\_GPE\\_L11\n") */
}

/* GPIO0 or GEvent8 event */
Method(_L18) {
/* DBGO("\\_GPE\\_L18\n") */
Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */
Notify(\_SB.PCI0.PBR8, 0x02) /* NOTIFY_DEVICE_WAKE */
}

/* SATA Controller PME# */
Method(_L1E) {
Notify(\_SB.PCI0.STCR, 0x02) /* NOTIFY_DEVICE_WAKE */
}


} /* End Scope GPE */
4 changes: 4 additions & 0 deletions src/mainboard/pcengines/apu2/mainboard.c
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Original file line number Diff line number Diff line change
Expand Up @@ -454,6 +454,10 @@ static void mainboard_final(void *chip_info)
gpio_set(GPIO_58, 1);
gpio_set(GPIO_59, 1);

/* Clear ACPI events */
outw(inw(ACPI_PM_EVT_BLK), ACPI_PM_EVT_BLK);
outl(inl(ACPI_GPE0_BLK), ACPI_GPE0_BLK);

if (!check_console()) {
/*The console is disabled, check if S1 is pressed and enable if so */
#if CONFIG(BOARD_PCENGINES_APU5)
Expand Down
4 changes: 0 additions & 4 deletions src/northbridge/amd/pi/00730F01/acpi/northbridge.asl
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Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,6 @@ Device(AMRT) {
Name(_ADR, 0x00000000)
} /* end AMRT */

Device(PCSD) { /* Processor configuration space devices */
Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */
}

/* Gpp 0 */
Device(PBR4) {
Name(_ADR, 0x00020001)
Expand Down
1 change: 1 addition & 0 deletions src/southbridge/amd/pi/hudson/acpi/fch.asl
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Expand Up @@ -23,6 +23,7 @@ Method(_OSC,4)
/* 0:11.0 - SATA */
Device(STCR) {
Name(_ADR, 0x00110000)
Name(_PRW, Package() {0x1e, 3})
} /* end STCR */

/* 0:14.0 - SMBUS */
Expand Down
54 changes: 9 additions & 45 deletions src/southbridge/amd/pi/hudson/acpi/usb.asl
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Original file line number Diff line number Diff line change
@@ -1,61 +1,25 @@
/* SPDX-License-Identifier: GPL-2.0-only */

/* 0:12.0 - OHCI */
Device(UOH1) {
/* 0:12.0 - EHCI */
Device(EHC1) {
Name(_ADR, 0x00120000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH1 */
} /* end EHC1 */

/* 0:12.2 - EHCI */
Device(UOH2) {
Name(_ADR, 0x00120002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH2 */

/* 0:13.0 - OHCI */
Device(UOH3) {
/* 0:13.0 - EHCI */
Device(EHC2) {
Name(_ADR, 0x00130000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH3 */
} /* end EHC2 */

/* 0:13.2 - EHCI */
Device(UOH4) {
Name(_ADR, 0x00130002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH4 */

/* 0:16.0 - OHCI */
Device(UOH5) {
/* 0:16.0 - EHCI */
Device(EHC3) {
Name(_ADR, 0x00160000)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */

/* 0:16.2 - EHCI */
Device(UOH6) {
Name(_ADR, 0x00160002)
Name(_PRW, Package() {0x0B, 3})
} /* end UOH5 */

#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \
!CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/* 0:14.5 - OHCI */
Device(UEH1) {
Name(_ADR, 0x00140005)
Name(_PRW, Package() {0x0B, 3})
} /* end UEH1 */
#endif
} /* end EHC3 */

/* 0:10.0 - XHCI 0*/
Device(XHC0) {
Name(_ADR, 0x00100000)
Name(_PRW, Package() {0x0B, 4})
} /* end XHC0 */

#if !CONFIG(SOUTHBRIDGE_AMD_PI_AVALON) && \
!CONFIG(SOUTHBRIDGE_AMD_PI_KERN)
/* 0:10.1 - XHCI 1*/
Device(XHC1) {
Name(_ADR, 0x00100001)
Name(_PRW, Package() {0x0B, 4})
} /* end XHC1 */
#endif