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arch-riscv: Add align and overlap constraints #18

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arch-riscv: Add align and overlap constraints #18

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43b6339
arch-riscv: Add align and overlap constraints
FanYang98 Nov 7, 2022
b0e99fa
arch-riscv:fix checked_vtype
FanYang98 Feb 21, 2023
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8 changes: 4 additions & 4 deletions src/arch/riscv/insts/vector.hh
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Original file line number Diff line number Diff line change
Expand Up @@ -79,8 +79,8 @@ class VConfOp : public RiscvStaticInst
std::string generateZimmDisassembly() const;
};

inline uint8_t checked_vtype(bool vill, uint8_t vtype) {
panic_if(vill, "vill has been set");
inline uint8_t checked_vtype(uint8_t opcode7, bool vill, uint8_t vtype) {
if (opcode7!=7&&opcode7!=39) panic_if(vill, "vill has been set");
const uint8_t vsew = bits(vtype, 5, 3);
panic_if(vsew >= 0b100, "vsew: %#x not supported", vsew);
const uint8_t vlmul = bits(vtype, 2, 0);
Expand All @@ -97,7 +97,7 @@ class VectorNonSplitInst : public RiscvStaticInst
OpClass __opClass)
: RiscvStaticInst(mnem, _machInst, __opClass),
vl(_machInst.vl),
vtype(checked_vtype(_machInst.vill, _machInst.vtype8))
vtype(checked_vtype(_machInst.opcode7,_machInst.vill,_machInst.vtype8))
{
this->flags[IsVector] = true;
}
Expand All @@ -115,7 +115,7 @@ class VectorMacroInst : public RiscvMacroInst
OpClass __opClass)
: RiscvMacroInst(mnem, _machInst, __opClass),
vl(_machInst.vl),
vtype(checked_vtype(_machInst.vill, _machInst.vtype8))
vtype(checked_vtype(_machInst.opcode7,_machInst.vill,_machInst.vtype8))
{
this->flags[IsVector] = true;
}
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1 change: 0 additions & 1 deletion src/arch/riscv/isa/decoder.isa
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Original file line number Diff line number Diff line change
Expand Up @@ -2461,7 +2461,6 @@ decode QUADRANT default Unknown::unknown() {
}}, OPFVV, VectorFloatArithOp);
}
}

format VectorFloatMaskFormat {
0x18: vmfeq_vv({{
Vd_ub[(i + offset)/8] = ASSIGN_VD_BIT(i + offset,
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