logic: Evaluate conditionals in dedicated frames

This prevents some name conflicts on generated bimpl nodes from within the evaluation of the conditional. Signed-off-by: Martin Povišer <[email protected]>
povik · Jan 3, 2024 · 34f4825 · 34f4825
1 parent 1b95893
commit 34f4825
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/fold/logic/design.py b/fold/logic/design.py
@@ -799,7 +799,11 @@ def impl_top_expr(self, lhslist, rhs, embedded=False):
 
     def eval_cond(self, ast):
         m = self.d.rtl_module
-        cond_sig = rtl.REDUCE_BOOL(m, self.eval(ast).extract_signal())
+        seq = BlockSeq(self.d, self.f)
+        stalk = self.immutlink(self.curr, seq.entry)
+        self.mutlink(self.curr, seq.entry, stalk, hot=rtl.HIGH)
+        cond_sig = rtl.REDUCE_BOOL(m, seq.eval(ast).extract_signal())
+        seq.finalize()
         with rtl.SynthAttrContext(src=markers_str(ast.markers)):
             rtl.ASSERT(m,
                 self.curr.en,